US4302845A
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US
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Phase-encoded data signal demodulator
Assignee: Motorola Solutions Inc
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Filing: 1980-02-07
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Granted: 1981-11-24
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Expires: 2000-02-07
Abstract
Abstract A demodulator is described for demodulating phase-encoded data signals transmitted on a noisy communication channel, such as, for example, radio communication channels of a radio communication system. The demodulator includes a digital phase-locked loop for phase-locking to the mid-bit transitions of the phase-encoded data signal, which, in the preferred embodiment is encoded according to the well known Manchester coding format, and further includes demodulating circuitry for sampling the phase-encoded data signal a predetermind number of times, weighting the samples according to predetermined weighting factors, totalizing the weighted samples for each bit interval and comparing the totalized samples to a predetermined threshold value for ascertaining the logical state of each bit of the phase-encoded data signal. For example, if the magnitude of the totalized samples is greater than or equal to the threshold value, a logical one state may be provided for the decoded data signal, and, if the magnitude of the totalized samples is less than the threshold value, a logical zero state may be provided for the decoded data signal. In preferred embodiments of the present invention, the weighting factors assigned to each sample may be either binary weighted or sine weighted, although any suitable weighting factors may be utilized depending on the characteristics of the phase-encoded data signal. The phase-encoded data signal demodulator embodying the present invention is particularly well adapted for demodulating high speed, phase-encoded data signals transmitted over radio channels to mobile and portable stations of a radio communication system.
Inventors
- 👤 Michael J. McClaughry
- 👤 John P. Byrns
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:03
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904; H04L25/02; H04L25/06; H04L25/068; H04L7/00; H04L7/02; H04L7/033; H04L7/0331
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
231 words
A demodulator for a phase-encoded data signal transmitted by a signal source at a predetermined bit frequency, comprising: means for generating a data clock signal, having successive cycle intervals at the predetermined bit frequency, and phase locking the generated data clock signal to the phase reversals of the phase-encoded data signal; means for multiplying the phase-encoded data signal and the data clock signal to provide an output signal having first and second states; means for sampling the state of the multiplying means output signal a predetermined number of times during each clock cycle interval to provide successive samples of the multiplying means output signal; means for weighting each sample of the multiplying means output signal occurring in the first half of each clock cycle interval according to corresponding predetermined weighting factors, and weighting each sample of the multiplying means output signal occurring in the second half of each clock cycle interval according to corresponding predetermined weighting factors; and means for totalizing the weighted samples of the multiplying means output signal for each clock cycle interval and providing a decoded data signal having a first state for each clock cycle interval where the magnitude of the totalized samples is at least as great as a predetermined threshold magnitude, and having a second state for each clock cycle interval where the magnitude of the totalized samples is less than the predetermined threshold magnitude.
Claim 2
Dependent Claim
231 words
A demodulator for a phase-encoded data signal transmitted by a signal source at a predetermined bit frequency, comprising: means for generating a data clock signal, having successive cycle intervals at the predetermined bit frequency, and phase locking the generated data clock signal to the phase reversals of the phase-encoded data signal; means for multiplying the phase-encoded data signal and the data clock signal to provide an output signal having first and second states; means for sampling the state of the multiplying means output signal a predetermined number of times during each clock cycle interval to provide successive samples of the multiplying means output signal; means for weighting each sample of the multiplying means output signal occurring in the first half of each clock cycle interval according to corresponding predetermined weighting factors, and weighting each sample of the multiplying means output signal occurring in the second half of each clock cycle interval according to corresponding predetermined weighting factors; and means for totalizing the weighted samples of the multiplying means output signal for each clock cycle interval and providing a decoded data signal having a first state for each clock cycle interval where the magnitude of the totalized samples is at least as great as a predetermined threshold magnitude, and having a second state for each clock cycle interval where the magnitude of the totalized samples is less than the predetermined threshold magnitude.
Claim 3
Dependent Claim
46 words
The demodulator according to claim 1, wherein the predetermined weighting factors for samples occurring in the second half of each clock cycle interval have a magnitude greater than that of the predetermined weighting factors for samples occurring in the first half of each clock cycle interval.
Claim 4
Dependent Claim
46 words
The demodulator according to claim 1, wherein the predetermined weighting factors for samples occurring in the first half of each clock cycle interval have a magnitude greater than that of the predetermined weighting factors for samples occurring in the second half of each clock cycle interval.
Claim 5
Dependent Claim
35 words
The demodulator according to claim 1, 2 or 3, wherein the predetermined weighting factors are sine weighted over the first half of each clock cycle interval and over the second half of each clock signal.
Claim 6
Dependent Claim
60 words
The demodulator according to claim 1, wherein said data clock signal generating and phase-locking means comprises a signal source for providing a reference clock signal having a frequency that is a preselected multiple of the predetermined bit frequency, and digital phase-locked loop means coupled to the reference clock signal and phase-encoded data signal for providing the phase-locked data clock signal.
Claim 7
Dependent Claim
41 words
The demodulator according to claim 1, wherein said weighting means includes memory means for storing the predetermined weighting factors for each sample, the weighting means responsive to each sample for reading out of the memory means its corresponding predetermined weighting factor.
Claim 8
Dependent Claim
43 words
The demodulator according to claim 1 or 6, wherein said totalizing means includes register means for storing the totalized samples during each clock cycle interval and adding means for successively adding each weighted sample to the totalized samples stored in the register means.
Claim 9
Dependent Claim
117 words
The demodulator according to claim 1, wherein said totalizing means totalizes the weighted samples from the first half and from the second half of each cycle interval and provides a decoded data signal having a first state for a clock cycle interval when the magnitudes of the totalized samples for both the first and second halves of the clock cycle interval are at least as great as first and second predetermined threshold magnitudes, respectively, and provides a decoded data signal having a second state when the magnitudes of the totalized samples for at least one of the first and second halves of the clock cycle interval is less than the first and second predetermined threshold magnitudes, respectively.
Claim 10
Dependent Claim
41 words
The demodulator according to claim 1, 2, 3, 5, 6 or 8 adapted for use in mobile and portable stations of a radio communication system, having at least one radio channel, for demodulating phase-encoded data signals transmitted on the radio channel.
Claim 11
Dependent Claim
252 words
A demodulator for a phase-encoded data signal transmitted by a signal source at a predetermined bit frequency, comprising: signal source means for generating a reference clock signal; digital phase-locked loop means responsive to the reference clock signal for generating a data clock signal, having successive clock cycle intervals at the predetermined bit frequency, and phase-locking the generated data clock signal to the phase reversals of the phase-encoded data signal; means for multiplying the phase-encoded data signal and the data clock signal to provide an output signal having first and second states; means for sampling the state of the multiplying means output signal a predetermined number of times during each clock cycle interval to provide successive samples of the multiplying means output signal; means for counting for each bit interval the samples of the multiplying means output signal having the first state and providing a totalized count for the first half and second half of each clock cycle interval, and means for providing a decoded data signal having a first state for each clock cycle interval where the magnitudes of the totalized counts for the first half and second half of a clock cycle interval is at least as great as a first and second predetermined threshold magnitude, respectively, and having a second state for each clock cycle interval where the magnitudes of the totalized counts for at least one of the first half and second half of a clock cycle interval is less than the first and second predetermined threshold magnitudes, respectively.
Claim 12
Dependent Claim
252 words
A demodulator for a phase-encoded data signal transmitted by a signal source at a predetermined bit frequency, comprising: signal source means for generating a reference clock signal; digital phase-locked loop means responsive to the reference clock signal for generating a data clock signal, having successive clock cycle intervals at the predetermined bit frequency, and phase-locking the generated data clock signal to the phase reversals of the phase-encoded data signal; means for multiplying the phase-encoded data signal and the data clock signal to provide an output signal having first and second states; means for sampling the state of the multiplying means output signal a predetermined number of times during each clock cycle interval to provide successive samples of the multiplying means output signal; means for counting for each bit interval the samples of the multiplying means output signal having the first state and providing a totalized count for the first half and second half of each clock cycle interval, and means for providing a decoded data signal having a first state for each clock cycle interval where the magnitudes of the totalized counts for the first half and second half of a clock cycle interval is at least as great as a first and second predetermined threshold magnitude, respectively, and having a second state for each clock cycle interval where the magnitudes of the totalized counts for at least one of the first half and second half of a clock cycle interval is less than the first and second predetermined threshold magnitudes, respectively.
Claim 13
Dependent Claim
320 words
A demodulator for a phase-encoded data signal transmitted by a signal source at a predetermined bit frequency, comprising: signal source means for generating a reference clock signal; digital phase-locked loop means responsive to the reference clock signal for generating a data clock signal, having successive clock cycle intervals at the predetermined bit frequency, and phase-locking the generated data clock signal to the phase reversals of the phase-encoded data signal; means for multiplying the phase-encoded data signal and the data clock signal to provide an output signal having first and second states; means for sampling the state of the multiplying means output signal N times during the first and second half of each clock cycle interval to provide successive samples of the multiplying means output signal, where N is an integer number greater than two (2); means for counting for each bit interval the samples of the multiplying means output signal having the first state and providing a totalized count for the first half and the combined first and second halves of each clock interval; and means for providing a decoded data signal having a first state for each clock interval where the magnitude of the totalized count for the combined first and second halves of a clock cycle interval is greater than N and where the totalized count for the combined first and second halves of a clock cycle interval is N and the totalized count for the first half of the clock cycle interval is less than one-half N, and having a second state for each clock cycle interval where the magnitude of the totalized count for the combined first and second halves of a clock cycle interval is less than and where the totalized count for the first and second halves of a clock cycle interval is equal to N and the totalized count for the first half of the clock cycle interval is greater than one-half N.
Claim 14
Dependent Claim
320 words
A demodulator for a phase-encoded data signal transmitted by a signal source at a predetermined bit frequency, comprising: signal source means for generating a reference clock signal; digital phase-locked loop means responsive to the reference clock signal for generating a data clock signal, having successive clock cycle intervals at the predetermined bit frequency, and phase-locking the generated data clock signal to the phase reversals of the phase-encoded data signal; means for multiplying the phase-encoded data signal and the data clock signal to provide an output signal having first and second states; means for sampling the state of the multiplying means output signal N times during the first and second half of each clock cycle interval to provide successive samples of the multiplying means output signal, where N is an integer number greater than two (2); means for counting for each bit interval the samples of the multiplying means output signal having the first state and providing a totalized count for the first half and the combined first and second halves of each clock interval; and means for providing a decoded data signal having a first state for each clock interval where the magnitude of the totalized count for the combined first and second halves of a clock cycle interval is greater than N and where the totalized count for the combined first and second halves of a clock cycle interval is N and the totalized count for the first half of the clock cycle interval is less than one-half N, and having a second state for each clock cycle interval where the magnitude of the totalized count for the combined first and second halves of a clock cycle interval is less than and where the totalized count for the first and second halves of a clock cycle interval is equal to N and the totalized count for the first half of the clock cycle interval is greater than one-half N.
Claim 15
Dependent Claim
35 words
The demodulator according to claim 11 adapted for use in mobile and portable stations of a radio communication system, having at least one radio channel, for demodulating phase-encoded data signals transmitted on the radio channel.
Claim 16
Dependent Claim
35 words
The demodulator according to claim 10 adapted for use in mobile and portable stations of a radio communication system, having at least one radio channel, for demodulating phase-encoded data signals transmitted on the radio channel.
Claim 17
Dependent Claim
234 words
A demodulator for a phase-encoded data signal transmitted by a signal source at a predetermined bit frequency, comprising: signal source means for providing a reference clock signal; digital phase-locked loop means responsive to the reference clock signal for generating a data clock signal, having successive clock cycle intervals at the predetermined bit frequency, and phase-locking the generated data clock signal to the phase reversals of the phase-encoded data signal; means for multiplying the phase-encoded data signal and the data clock signal to provide an output signal having first and second states; means for sampling the state of the multiplying means output signal a predetermined number of times during each clock cycle interval to provide successive samples of the multiplying means output signal; means for storing a predetermined weighting factor associated with each sample taken during successively clock cycle intervals; means responsive to each sample of the multiplying means output signal having the first state for reading out from the storing means the corresponding predetermined weighting factor; means for totalizing the read-out predetermined weighting factors; and means for providing a decoded data signal having a first state for each clock cycle interval where the magnitude of the totalized weighting factors is at least as great as a predetermined threshold magnitude, and providing a second state for each clock cycle interval where the magnitude of the totalized weighting factors is less than the predetermined threshold magnitude.
Claim 18
Dependent Claim
234 words
A demodulator for a phase-encoded data signal transmitted by a signal source at a predetermined bit frequency, comprising: signal source means for providing a reference clock signal; digital phase-locked loop means responsive to the reference clock signal for generating a data clock signal, having successive clock cycle intervals at the predetermined bit frequency, and phase-locking the generated data clock signal to the phase reversals of the phase-encoded data signal; means for multiplying the phase-encoded data signal and the data clock signal to provide an output signal having first and second states; means for sampling the state of the multiplying means output signal a predetermined number of times during each clock cycle interval to provide successive samples of the multiplying means output signal; means for storing a predetermined weighting factor associated with each sample taken during successively clock cycle intervals; means responsive to each sample of the multiplying means output signal having the first state for reading out from the storing means the corresponding predetermined weighting factor; means for totalizing the read-out predetermined weighting factors; and means for providing a decoded data signal having a first state for each clock cycle interval where the magnitude of the totalized weighting factors is at least as great as a predetermined threshold magnitude, and providing a second state for each clock cycle interval where the magnitude of the totalized weighting factors is less than the predetermined threshold magnitude.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-11-23 | 1985-05-25 | 1985-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-11-23 | 1989-05-25 | 1989-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-11-23 | 1993-05-25 | 1993-11-24 | $7700.00 | Window Closed / Lapsed |