Ratioless FET programmable logic array

Claim 1

A logic array including a plurality of FETs connected in sets to perform AND functions and OR functions, each FET having a gate and first and second conducting regions, the gates of said AND FETs serving as inputs for said logic array, a separate column conductor for each AND set connecting together one of the conducting regions of each FET in its associated and set, a separate row conductor for each OR set connecting together the first conducting region of each FET in its associated OR set, a common conductor connecting together second conducting regions of all FETs performing an OR function, precharging means precharging said column conductors, said row conductors and said common conductor, and selection means selecting a particular combination of one or more AND sets for operation in conjunction with the operation of one or more OR sets in accordance with a particular function it is desired that the array perform, said selection means connected to said common conductor including delay means delaying the operation of all said one or more OR sets associated with a particular function until said selected one or more AND sets associated with that function have all operated.