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US4634890A
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Clamping circuit finding particular application between a single sided output of a computer memory and a differential amplifier sensing circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1984-09-06
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Granted: 1987-01-06
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Expires: 2004-09-06
Abstract
Abstract A transistor arrangement for clamping the output node of a semiconductor memory, including an inverter to parallel with a transmission gate for producing a differential output signal.
Inventors
- 👤 Robert D. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:48
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4094; G11C7/00; G11C7/12
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
132 words
A clamping circuit for connection between a single sided output of a memory and the twin inputs of a differential amplifier sensing circuit comprising: a CMOS inverter including a pair of complementary transistors serially connected and an output at the node between the two transistors with the input of each transistor coupled to the single sided output, a first transmission gate whose input is connected to the single-sided output and whose output is connected to the output of the inverter, a second transmission gate whose input is connected to the output of the invertor and whose output is connected to one of the twin inputs of the differential amplifier, the other of the twin inputs being connected to said single-sided output; and means for synchronously enabling the first and second transmission gates.
Claim 2
Dependent Claim
132 words
A clamping circuit for connection between a single sided output of a memory and the twin inputs of a differential amplifier sensing circuit comprising: a CMOS inverter including a pair of complementary transistors serially connected and an output at the node between the two transistors with the input of each transistor coupled to the single sided output, a first transmission gate whose input is connected to the single-sided output and whose output is connected to the output of the inverter, a second transmission gate whose input is connected to the output of the invertor and whose output is connected to one of the twin inputs of the differential amplifier, the other of the twin inputs being connected to said single-sided output; and means for synchronously enabling the first and second transmission gates.
Claim 3
Dependent Claim
12 words
The clamping circuit of claim 1 in combination with said differential amplifier.
Claim 4
Dependent Claim
21 words
The combination of claim 2 in which the differential amplifer is enabled in synchronism with the enabling of the transmission gates.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-05 | 1990-07-07 | 1991-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-05 | 1994-07-07 | 1995-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-05 | 1998-07-07 | 1999-01-06 | $7700.00 | Window Closed / Lapsed |