Patent US4628436A successfully refreshed from Google Patents.
US4628436A
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US
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Digital controller
Assignee: Hitachi Ltd
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Filing: 1984-02-22
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Granted: 1986-12-09
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Expires: 2004-02-22
Abstract
Abstract A digital controller for controlling a plurality of processes. In view of the fact that in case a plurality of processes of a like nature are to be controlled, same operands are used for performing a similar arithmetic operation a number of times, instructions are stored in a common memory for simplifying the programming, while the operands are stored in memories each incorporated in each of the processors adapted for controlling individually the objective processes, to thereby allow arithmetic processings to be performed by the processors in parallel with one another. Overall processing speed is made thus significantly high.
Inventors
- 👤 Tadashi Okamoto
- 👤 Hiromasa Yamaoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:46
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
272 words
A digital controller for controlling a plurality of objectives to be controlled, which objectives are of the same kind, wherein a plurality of processors are provided in correspondence to said plurality of objectives, comprising: an instruction memory for storing instruction codes which are provided as a common control program for controlling said plurality of processors to execute said objectives, and addresses of storage locations holding operand addresses associated with said instruction codes; common control means connected to said instruction memory and said plurality of processors for reading out an instruction code and the associated storage location address from said instruction memory to all of said processors, and for generating a parallel execution process signal in each of said processors to effect execution of said instruction code in parallel by said processors; an operand memory provided in each of said processors, each operand memory having storage locations storing operand addresses, which storage locations are accessed by the same storage location address read out from said instruction memory; and an input/output data buffer memory provided in each of said processors and operatively associated with the operand memory therein for storing data accessed by the operand addresses stored in said operand memory; wherein a similar operation is carried out in each of said processors in parallel in response to the same instruction code read out from said instruction memory and data accessed from the input/output data buffer memory provided in each of the processors on the basis of the operand address which is obtained by accessing the operand memory with the storage location address associated with the instruction code read out of said instruction memory.
Claim 2
Dependent Claim
272 words
A digital controller for controlling a plurality of objectives to be controlled, which objectives are of the same kind, wherein a plurality of processors are provided in correspondence to said plurality of objectives, comprising: an instruction memory for storing instruction codes which are provided as a common control program for controlling said plurality of processors to execute said objectives, and addresses of storage locations holding operand addresses associated with said instruction codes; common control means connected to said instruction memory and said plurality of processors for reading out an instruction code and the associated storage location address from said instruction memory to all of said processors, and for generating a parallel execution process signal in each of said processors to effect execution of said instruction code in parallel by said processors; an operand memory provided in each of said processors, each operand memory having storage locations storing operand addresses, which storage locations are accessed by the same storage location address read out from said instruction memory; and an input/output data buffer memory provided in each of said processors and operatively associated with the operand memory therein for storing data accessed by the operand addresses stored in said operand memory; wherein a similar operation is carried out in each of said processors in parallel in response to the same instruction code read out from said instruction memory and data accessed from the input/output data buffer memory provided in each of the processors on the basis of the operand address which is obtained by accessing the operand memory with the storage location address associated with the instruction code read out of said instruction memory.
Claim 3
Dependent Claim
59 words
A digital controller according to claim 1, further including dual-port memories for outputting the results of said parallel processings, and local buses provided for each of said processors for coupling said processors to said dual-port memories, respectively, wherein the results of said processings performed by each of the processors are fetched by the other processors through said local buses.
Claim 4
Dependent Claim
38 words
A digital controller according to claim 1, wherein a storage location in the form of a dummy register is assigned in the operand memory in the processor for which no data is required for the parallel arithmetic processing.
References Cited (Backward Citations)
US3364472A
Cited
US3787673A
Cited
GB1456941A
Cited
US4128876A
Cited
US4366535A
Cited
US4438488A
Cited
US4338675A
Cited
US4428043A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-08 | 1990-06-09 | 1990-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-08 | 1994-06-09 | 1994-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-08 | 1998-06-09 | 1998-12-09 | $7700.00 | Window Closed / Lapsed |