Power conserving CMOS reference voltage source

Claim 1

A power-conserving CMOS reference voltage generation circuit comprising first (101) and second (101') parallel reference voltage sources, coupled to a common ENABLE input, and having a common reference voltage output node (101"), each source including a first, p-channel (102,102') and a second, n-channel (103,103') CMOS transistor series-connected between Vcc and ground, said first and second transistors having respective gates connected at a common gate node (G, G') and respective drains connected to a common drain node (D, D'), characterized in that: said second reference voltage source (101') is of relatively large capacity compared to said first source (101), means (173, 107'), responsive to a rising signal edge at said ENABLE input, are provided for temporarily enabling said second source (101'), thereby shortening the time required to drive the reference voltage at said output node (101") to a desired level, i.e. enhancing the slew rate of said node, and means (190-194) are provided for interconnecting said common gate nodes (G,G'), said common drain nodes (D,D'), and said common output reference voltage output node (101") in response to a high signal on said ENABLE input and for isolating said nodes from one another in response to a low signal on said ENABLE input, thereby conserving power.