Automatic assembly of integrated circuits

Claim 1

A method of processing semiconductor integrated circuit devices comprising the steps of: a. applying a dielectric top coating having a top surface over at least two integrated circuits on a wafer; b. forming at least two arrays of conductive leads from predetermined nodes of said integrated circuits along said top surface of said dielectric top coating to at least two corresponding predetermined arrays of electrical contacts disposed on said top surface of said dielectric above each of said at least two circuits; c. separating said at least two circuits to form at least two circuit chips by cutting entirely through said wafer while leaving a cover portion of said dielectric above each of said integrated circuits and below said standard arrays; d. removing a selected chip from said at least two circuit chips by striking an adhesive support member having an adhesive side to which said selected chip is attached and an opposite side at a point on said opposite side opposite said selected chip, thereby releasing said chip from said adhesive; e. positioning a leadframe, having an array of contact members disposed in a lead contact array positionally matching said predetermined array of electrical contacts, in alignment with said selected chip so that said lead contact array touches said array of electrical contacts, said at least two predetermined arrays of electrical contacts being sized to fit on at least two different integrated circuit chips so that said leadframe may be used with more than one integrated circuit; and f. conductively bonding at least two of said array of electrical contracts to said lead contact array simultaneously.

Claim 2

A method of processing semiconductor integrated circuit devices comprising the steps of: a. applying a dielectric top coating having a top surface over at least two integrated circuits on a wafer; b. forming at least two arrays of conductive leads from predetermined nodes of said integrated circuits along said top surface of said dielectric top coating to at least two corresponding predetermined arrays of electrical contacts disposed on said top surface of said dielectric above each of said at least two circuits; c. separating said at least two circuits to form at least two circuit chips by cutting entirely through said wafer while leaving a cover portion of said dielectric above each of said integrated circuits and below said standard arrays; d. removing a selected chip from said at least two circuit chips by striking an adhesive support member having an adhesive side to which said selected chip is attached and an opposite side at a point on said opposite side opposite said selected chip, thereby releasing said chip from said adhesive; e. positioning a leadframe, having an array of contact members disposed in a lead contact array positionally matching said predetermined array of electrical contacts, in alignment with said selected chip so that said lead contact array touches said array of electrical contacts, said at least two predetermined arrays of electrical contacts being sized to fit on at least two different integrated circuit chips so that said leadframe may be used with more than one integrated circuit; and f. conductively bonding at least two of said array of electrical contracts to said lead contact array simultaneously.