Patent US3105231A successfully refreshed from Google Patents.
Patent US4625313A successfully refreshed from Google Patents.
US4625313A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for testing electronic equipment
Assignee: Techsearch LLC
•
Filing: 1984-07-06
•
Granted: 1986-11-25
•
Expires: 2004-07-06
Abstract
Abstract A microprocessor-based apparatus for testing the electrical condition of electronic circuitry, particularly computers, employs a buffer and a latch associated with each of the address bus and the data bus to provide electrical isolation of said buses. In using the apparatus, the integrity of a central testing "kernel" comprising the testing program itself with its testing data in ROM is first verified. The testing program then evaluates, in order, the data bus, the address bus, and then such additional and addressable circuitry as may be connected to said data bus and address bus. Incorporation of analog-to-digital converters permits determination of actual circuit node voltages, in addition to digital levels or the presence of open or short circuits.
Inventors
- 👤 Richard A. Springer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:58
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/221; G06F11/2236
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
227 words
Digital apparatus comprising: a microprocessor; a first address bus portion connected to said microprocessor; a first data bus portion connected to said microprocessor; digital memory connected between said first address bus portion and said first data bus portion; a second address bus portion; address buffer means which connect said first address bus portion to said second address bus portion, so as to isolate electrically said first address bus portion from said second address bus portion, but permitting the transfer of electrical signals at least from said first address bus portion to said second address bus portion; a second data bus portion; data buffer means which connect said first data bus portion to said second data bus portion, so as to isolate electrically said first data bus portion, but permitting the transfer of electrical signals both from said first data bus portion to said second data bus portion, and from said second data bus portion to said first data bus portion; and data latch means which connect from said first data bus portion to said second data bus portion, so as to isolate electrically said first data bus portion from said second data bus portion, but permitting the capture by said data latch means of electrical signals at least from said first data bus portion and the application of captured electrical signals to said second data bus portion.
Claim 2
Dependent Claim
227 words
Digital apparatus comprising: a microprocessor; a first address bus portion connected to said microprocessor; a first data bus portion connected to said microprocessor; digital memory connected between said first address bus portion and said first data bus portion; a second address bus portion; address buffer means which connect said first address bus portion to said second address bus portion, so as to isolate electrically said first address bus portion from said second address bus portion, but permitting the transfer of electrical signals at least from said first address bus portion to said second address bus portion; a second data bus portion; data buffer means which connect said first data bus portion to said second data bus portion, so as to isolate electrically said first data bus portion, but permitting the transfer of electrical signals both from said first data bus portion to said second data bus portion, and from said second data bus portion to said first data bus portion; and data latch means which connect from said first data bus portion to said second data bus portion, so as to isolate electrically said first data bus portion from said second data bus portion, but permitting the capture by said data latch means of electrical signals at least from said first data bus portion and the application of captured electrical signals to said second data bus portion.
Claim 3
Dependent Claim
75 words
The apparatus of claim 1, further comprising address latch means which connect from said second address bus portion to said second data bus portion, so as to isolate electrically said second address bus portion from said second data bus portion, but permitting the capture by said address latch means of electrical signals from said second address bus portion, and further permitting the reading through said second data bus portion of the electrical signals so captured.
Claim 4
Dependent Claim
141 words
Digital apparatus comprising: a microprocessor; a first bus section connected to said microprocessor; digital memory connected to said first bus section; a second bus section; buffer means which connect said first bus section to said second bus section, so as to isolate electrically said first bus section from said second bus section, but permitting the transfer of electrical signals both from said first bus section to said second bus section and from said second bus section to said first bus section; and latch means which connect from said first bus section to said second bus section, so as to permit the capture of electrical signals from said first bus section and the application of captured electrical signals to said second bus section without use of the buffer means and while isolating electrically the first bus section from the second bus section.
Claim 5
Dependent Claim
141 words
Digital apparatus comprising: a microprocessor; a first bus section connected to said microprocessor; digital memory connected to said first bus section; a second bus section; buffer means which connect said first bus section to said second bus section, so as to isolate electrically said first bus section from said second bus section, but permitting the transfer of electrical signals both from said first bus section to said second bus section and from said second bus section to said first bus section; and latch means which connect from said first bus section to said second bus section, so as to permit the capture of electrical signals from said first bus section and the application of captured electrical signals to said second bus section without use of the buffer means and while isolating electrically the first bus section from the second bus section.
Claim 6
Dependent Claim
255 words
Digital apparatus according to claim 3, wherein the first and second bus sections each comprise a portion of an address bus and a portion of a data bus, said buffer means comprise data buffer means which connect the two portions of the data bus, and said latch means comprise data latch means which connect from the data bus portion of the first bus section to the data bus portion of the second bus section, and the apparatus further comprises address buffer means which connect the two portions of the address bus so as to isolate the address bus portion of the first bus section from the address bus portion of the second bus section but permit the transfer of electrical signals at least from the address bus portion of the first bus section to the address bus portion of the second bus section, digital memory connected between the address bus portion of the first bus section and the data bus portion of the first bus section, and address latch means which connect from the address bus portion of the second bus section to the data bus portion of the second bus section, so as to isolate electrically the address bus portion of the second bus section from the data bus portion of the second bus section but permit the capture by the address latch means of electrical signals from the address bus portion of the second bus section and the application of captured electrical signals to the data bus portion of the second bus section.
Claim 7
Independent Claim
252 words
A method for testing the electrical condition of an electronic circuit that comprises a microprocessor, a first bus section connected to the microprocessor, a second bus section, buffer means having a first side connected to said first bus section and a second side connected to said second bus section so as to isolate electrically said first bus section from said second bus section but permit the transfer of electrical signals both from said first bus section to said second bus section and from said second bus section to said first bus section, the method comprising the steps of a. conducting a verification test upon a digital memory that is connected to the first bus section and wherein there is stored a body of test data, in order to determine whether the digital memory is properly programmed and whether the microprocessor, the first bus section and the first side of the buffer means are functioning properly; b. if the verification test confirms that the digital memory is properly programmed and that the microprocessor, the first bus section and the first side of the buffer means are functioning properly, transferring a portion of said test data to the second bus section by way of latch means that connect said first bus section to said second bus section without use of the buffer means, receiving a portion of response data back from the second bus section by way of the buffer means, and comparing said portion of response data to said portion of test data.
Claim 8
Independent Claim
252 words
A method for testing the electrical condition of an electronic circuit that comprises a microprocessor, a first bus section connected to the microprocessor, a second bus section, buffer means having a first side connected to said first bus section and a second side connected to said second bus section so as to isolate electrically said first bus section from said second bus section but permit the transfer of electrical signals both from said first bus section to said second bus section and from said second bus section to said first bus section, the method comprising the steps of a. conducting a verification test upon a digital memory that is connected to the first bus section and wherein there is stored a body of test data, in order to determine whether the digital memory is properly programmed and whether the microprocessor, the first bus section and the first side of the buffer means are functioning properly; b. if the verification test confirms that the digital memory is properly programmed and that the microprocessor, the first bus section and the first side of the buffer means are functioning properly, transferring a portion of said test data to the second bus section by way of latch means that connect said first bus section to said second bus section without use of the buffer means, receiving a portion of response data back from the second bus section by way of the buffer means, and comparing said portion of response data to said portion of test data.
Claim 9
Dependent Claim
230 words
A method according to claim 5, wherein said first bus section comprises a first address bus portion and a first data bus portion and said second bus section comprises a second address bus portion and a second data bus portion and the buffer means comprise a data buffer that connects the first data bus portion to the second data bus portion and permits the transfer of electrical signals both from the first data bus portion to said second data bus portion and from said second data bus portion to said first data bus portion, and the electronic circuit further comprises an address buffer that connects the first address bus portion to the second address bus portion and permits transfer of electrical signals at least from said first address bus portion to said second address bus portion, and wherein the method further comprises transferring a second portion of test data to the second address bus portion by way of the first address bus portion and the address buffer, capturing a second portion of response data from the second address bus portion by means of an address latch, transferring the second portion of response data from the address latch to the first data bus portion by way of the second data bus portion and the buffer means, and comparing the second portion of response data to the second portion of test data.
Claim 10
Independent Claim
139 words
A method for testing the electrical condition of a bus that comprises first and second bus sections and buffer means that connect the first and second bus sections so as to isolate the bus sections electrically but permit the transfer of electrical signals at least from the second bus section to the first bus section, the method comprising the steps of a. writing a test pattern into latch means that connect the first and second bus sections, said test pattern being written into the latch means without passing through the buffer means, b. reading a response pattern from the latch means onto the second bus section and transferring the response pattern to the first bus section by way of the buffer means, and c. comparing the response pattern as received on the first bus section with the test pattern.
Claim 11
Independent Claim
139 words
A method for testing the electrical condition of a bus that comprises first and second bus sections and buffer means that connect the first and second bus sections so as to isolate the bus sections electrically but permit the transfer of electrical signals at least from the second bus section to the first bus section, the method comprising the steps of a. writing a test pattern into latch means that connect the first and second bus sections, said test pattern being written into the latch means without passing through the buffer means, b. reading a response pattern from the latch means onto the second bus section and transferring the response pattern to the first bus section by way of the buffer means, and c. comparing the response pattern as received on the first bus section with the test pattern.
Claim 12
Dependent Claim
135 words
A method according to claim 7, wherein the first bus section comprises a first address bus portion and a first data bus portion, the second bus section comprises a second address bus portion and a second data bus portion, and the buffer means comprise a data buffer that connects the first and second data bus portions, and wherein the method further comprises writing a second test pattern into an address latch that connect the second address bus portion and the second data bus portion, reading a second response pattern from the address latch onto the second data bus portion, transferring the second response pattern to the first data bus portion by way of the buffer means, and comparing the second response pattern as received on the first data bus portion with the second test pattern.
References Cited (Backward Citations)
US3519808A
Cited
US3761695A
Cited
US4194113A
Cited
US4317200A
Cited
US4312067A
Cited
US4476431A
Cited
US4455654A
Cited
US4455654B1
Cited
US4503386A
Cited
US4493078A
Cited
US4519078A
Cited
US4534028A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-24 | 1990-05-26 | 1990-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-24 | 1994-05-26 | 1994-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-24 | 1998-05-26 | 1998-11-25 | $7700.00 | Window Closed / Lapsed |