Method and apparatus for testing a digital computer

Claim 3

The method defined in claim 1, wherein said monitoring step includes the steps of: (1) receiving said control signals during at least a part of the period of execution of said instruction; (2) repeatedly sampling said control signals at a plurality of time instants during said period; and (3) producing said first signature code in dependence upon the respective states of said control signals at said plurality of time instants.

Claim 4

The method defined in claim 2, wherein said digital computer further comprises a clock generator for producing a clock signal and wherein said monitoring step includes the step of sampling said control signals synchronously with said clock signal.

Claim 5

The method defined in claim 3, including the step of sampling said control signals a prescribed number of times each clock cycle except that the number of sampling times is always the same during read or write operations and independent of the length of time such read or write operations require.

Claim 6

The method defined in claim 2, wherein said monitoring step includes the step of monitoring said control signals additionally during the fetching of said instruction, such that said first signature corresponds to said control signals during both fetching and execution of said instruction.

Claim 7

The method defined in claim 1, wherein said receiving step includes the steps of: (1) determining from said operation code whether a conditional branch instruction is to be executed by said processor means; and (2) if a conditional branch instruction is to be executed, selecting and producing one of at least two possible second signature codes, in dependence upon which condition is satisfied.

Claim 8

The method defined in claim 1, further comprising the step of forcing said output signals into prescribed, desired states and thereafter carrying out said steps of monitoring said control signals and producing a signature code in response thereto, thereby to test the operation of said method of testing.

Claim 9

The method defined in claim 1, further comprising the step of watchdog timing the period between successive fetches of instructions, and setting said output signal to the error indicating state if said period exceeds a prescribed maximum time.

Claim 10

The method recited in claim 1, further comprising the steps of: (e) detecting the acknowledgement of an interrupt condition by said processor means; and (f) if said interrupt acknowledge condition is detected, selecting a second signature code which corresponds to the first signature code produced by the control signals during the interrupt acknowledgement cycle of the microprocessor.

Claim 11

Apparatus for testing a digital computer having (a) processor means for executing instructions and (b) memory means, associated with said processor means, for storing the instructions to be executed by said processor means, said instructions being selected from a prescribed set of instructions, each separate instruction in said set being defined by a unique operation code; wherein said processor means includes a plurality of control signal outputs and means for generating control signals at said outputs upon fetching and execution of each instruction in said set; said apparatus comprising, in combination: (a) control means coupled to said control signal outputs, for detecting when an operation code for an instruction to be executed by said processor means is fetched from said memory means; (b) first means, connected to said control signal outputs and responsive to said control means, for producing a first signature code in dependence upon said control signals during a prescribed period of time, wherein one unique first signature code corresponds to each unique set of control signals during said period of time; (c) second means, coupled to said memory means and responsive to said control means, for producing a second signature code in dependence upon the operation code of the instruction to be executed by said processor means, said second signature code corresponding to what said first signature code would be if said processor means were operating properly; and (d) third menas connected to said first and said second means for comparing said first and said second signature codes and producing an output signal indicative of error if they are unequal.

Claim 12

Apparatus for testing a digital computer having (a) processor means for executing instructions and (b) memory means, associated with said processor means, for storing the instructions to be executed by said processor means, said instructions being selected from a prescribed set of instructions, each separate instruction in said set being defined by a unique operation code; wherein said processor means includes a plurality of control signal outputs and means for generating control signals at said outputs upon fetching and execution of each instruction in said set; said apparatus comprising, in combination: (a) control means coupled to said control signal outputs, for detecting when an operation code for an instruction to be executed by said processor means is fetched from said memory means; (b) first means, connected to said control signal outputs and responsive to said control means, for producing a first signature code in dependence upon said control signals during a prescribed period of time, wherein one unique first signature code corresponds to each unique set of control signals during said period of time; (c) second means, coupled to said memory means and responsive to said control means, for producing a second signature code in dependence upon the operation code of the instruction to be executed by said processor means, said second signature code corresponding to what said first signature code would be if said processor means were operating properly; and (d) third menas connected to said first and said second means for comparing said first and said second signature codes and producing an output signal indicative of error if they are unequal.

Claim 13

The apparatus defined in claim 10, wherein said first means includes means for repeatedly sampling said control signals at a plurality of time instants, thereby to produce said first signature code in dependence upon the respective states of said control signals at plurality of time instants.

Claim 14

The apparatus defined in claim 11, wherein said digital computer further comprises a clock generator for producing a clock signal and said means for repeatedly sampling is responsive to said clock signal to sample said control signals synchronously with said clock signal.

Claim 15

The apparatus defined in claim 12, wherein said sampling means repeatedly samples said control signals a prescribed number of times each clock cycle except that the number of sampling times is always the same during read or write operations and independent of the length of time such read or write operations require.

Claim 16

The apparatus defined in claim 11, wherein said first means is a built-in logic block observer.

Claim 17

The apparatus defined in claim 10, wherein said second means includes combinational logic means for storing a plurality of said second signature codes.

Claim 18

The apparatus defined in claim 15, wherein said combinational logic means a read-only memory.

Claim 19

The apparatus defined in claim 15, wherein said second means includes (1) decoding means, coupled to said memory means and responsive to said control means, for determining from said operation code whether a conditional branch instruction is to be executed by said processor means; and (2) logic means, coupled to said decoding means, for selecting one of at least two possible second signature codes, in dependence upon which condition is satisfied.

Claim 20

The apparatus defined in claim 10, further comprising means for forcing said output signals into a prescribed, desired states, thereby to test the operation of said testing apparatus.

Claim 21

The apparatus defined in claim 10, further comprising means for initializing said first means to a prescribed, desired state upon detecting the fetching of the first instruction following an idle condition of said processor means.

Claim 22

The apparatus defined in claim 10, further comprising watchdog timer means, coupled to at least one of said control signal outputs and to said third means, for timing the period between successive fetches of instructions and setting said third means to the error-indicating state if said period exceeds a prescribed maximum time.

Claim 23

The apparatus recited in claim 10, further comprising logic means, coupled to at least one of said control signal outputs and to said third means, for detecting the acknowledgement of an interrupt condition by said processor means, and if said interrupt acknowledge condition is detected, selecting a second signature code which corresponds to the first signature code produced by the control signals during the interrupt acknowledgement cycle of the microprocessor.

Claim 26

The method defined in claim 23, wherein said monitoring step includes the steps of: (1) receiving said control signals during at least a part of the period of fetching of said instruction; (2) repeatedly sampling said control signals at a plurality of time instants during said period; and (3) producing said first signature code in dependence upon the respective states of said control signals at said plurality of time instants.

Claim 27

The method defined in claim 24, wherein said digital computer further comprises a clock generator for producing a clock signal and wherein said monitoring step includes the step of sampling said control signals synchronously with said clock signal.

Claim 28

The method defined in claim 25, including the step of sampling said control signals a prescribed number of times each clock cycle except that the number of sampling times is always the same during read or write operations and independent of the length of time such read or write operations require.

Claim 29

The method defined in claim 23, wherein said receiving step includes the steps of: (1) determining from said operation code whether a conditional branch instruction is to be executed by said processor means; and (2) if a conditional branch instruction is to be executed, selecting and producing one of at least two possible second signature codes, in dependence upon which condition is satisfied.

Claim 30

The method defined in claim 23, further comprising the step of forcing said output signals into prescribed, desired states and thereafter carrying out said steps of monitoring said control signals and producing a signature code in response thereto, thereby to test the operation of said method of testing.

Claim 31

The method defined in claim 23, further comprising the step of watchdog timing the period between successive fetches of instructions, and setting said output signal to the error-indicating state if said period exceeds a prescribed maximum time.

Claim 32

The method recited in claim 23, further comprising the steps of: (e) detecting the acknowledgement of an interrupt condition by said processor means; and (f) if said interrupt acknowledge condition is detected, selecting a second signature code which corresponds to the first signature code produced by the control signals during the interrupt acknowledgement cycle of the microprocessor.