Input circuit for charge transfer device

Claim 2

A charge coupled circuit wherein the potential barrier in the input gates is the same as in the transfer gates comprising a substrate of a first conductivity type, a layer of opposite conductivity type formed in the surface of said substrate, a plurality of transfer gates formed over said layer of opposite conductivity type and a plurality of transfer voltages alternately supplied to said transfer gates, a pair of adjacent input gates formed over a portion of said opposite conductivity type and the same variable input signal applied thereto, and an input region of opposite conductivity type formed in said substrate adjacent said pair of adjacent input gates.

Claim 3

A charge coupled device according to claim 1 wherein said layer of opposite conductivity type comprises alternate N- and N regions.

Claim 4

A charge coupled circuit wherein the potential barrier in the input gates is the same as in the transfer gates comprising a substrate of a first conductivity type, an insulating layer of alternating thicker portions and thinner portions formed on said substrate, a first plurality of transfer gates formed on said thicker portions and a second plurality of transfer gates formed on said thinner portions of said insulating layer, transfer voltages applied to said thicker portions and to said thinner portions with the same transfer voltage applied to one of said plurality of thicker portions and to one of said plurality of thinner portions, an input region of opposite conductivity type formed in said substrate and an input signal supplied thereto, and a pair of input gates formed on said insulating layer between said input region and said first and second plurality of transfer gates and the same variable input switching signals supplied thereto.

Claim 5

A charge coupled circuit wherein the potential barrier in the input gates is the same as in the transfer gates comprising a substrate of a first conductivity type, an insulating layer of alternating thicker portions and thinner portions formed on said substrate, a first plurality of transfer gates formed on said thicker portions and a second plurality of transfer gates formed on said thinner portions of said insulating layer, transfer voltages applied to said thicker portions and to said thinner portions with the same transfer voltage applied to one of said plurality of thicker portions and to one of said plurality of thinner portions, an input region of opposite conductivity type formed in said substrate and an input signal supplied thereto, and a pair of input gates formed on said insulating layer between said input region and said first and second plurality of transfer gates and the same variable input switching signals supplied thereto.

Claim 6

A charge coupled circuit wherein the potential barrier in the input gates is the same as in the transfer gates, comprising a substrate of a first conductivity type, a plurality of spaced regions of the same conductivity type formed in the surface of said substrate and having a higher impurity concentration than said substrate, a plurality of pairs of transfer gates formed on said substrate with one of each pair of said pairs of transfer gates formed over said spaced regions, a plurality of transfer voltages alternately applied to said pairs of transfer gates, a pair of adjacent input gates formed on said substrate with the first one of said pair of adjacent input gates formed over one of said plurality of spaced region and the same variable input signal applied to said pair of adjacent input gates, and an input region of opposite conductivity type formed in said substrate adjacent said pair of adjacent input gates.

Claim 7

A charge coupled circuit wherein the potential barrier in the input gates is the same as in the transfer gates, comprising a substrate of a first conductivity type, a plurality of spaced regions of the same conductivity type formed in the surface of said substrate and having a higher impurity concentration than said substrate, a plurality of pairs of transfer gates formed on said substrate with one of each pair of said pairs of transfer gates formed over said spaced regions, a plurality of transfer voltages alternately applied to said pairs of transfer gates, a pair of adjacent input gates formed on said substrate with the first one of said pair of adjacent input gates formed over one of said plurality of spaced region and the same variable input signal applied to said pair of adjacent input gates, and an input region of opposite conductivity type formed in said substrate adjacent said pair of adjacent input gates.