Charge transfer output circuits

Claim 2

An output circuit for a charge transfer circuit in which there is an output location which includes an electrically floating region whose potential is affected when a charge signal is shifted to said output location, said circuit comprising: a semiconductor substrate of given conductivity type; first electrode means electrically connected to said floating region, said first electrode means being insulated from the substrate and being responsive to the voltage at said floating region for producing a substrate potential proportional thereto; first and second regions in the substrate of opposite conductivity type than the substrate, both spaced from said first electrode means, each such region being independent of said electrically floating region; second and third electrode means, both insulated from said substrate and from said first electrode means, said second electrode means extending between said first region and first electrode means for controlling, in response to a signal first control voltage whose level can be controlled, the transfer of charge between said first region and a substrate region beneath said first electrode means, and said third electrode means extending between said second region and said first electrode means for controlling, in response to a single second control voltage whose level can be controlled, the transfer of charge between said second region and said substrate region beneath said first electrode means; and means for applying potentials to said first and second regions for permitting each to operate as a source of charge carriers for said substrate region beneath said first electrode means, the passage of such charge carriers being under the control of said second and third electrode means, respectively, and for applying potentials to said first and second regions for permitting each to operate as a drain for charge carriers from the substrate region beneath said first electrode means, the passage of such charge carriers being under the control of said second and third electrode means, respectively.

Claim 3

An output circuit as set forth in claim 1, further including means for applying one of: a) said first control voltage at a level to form a conduction path in the substrate beneath said second electrode means to thereby permit the flow of charge and for concurrently applying said second control voltage at a level to form a potential barrier in the substrate beneath said third electrode means to thereby prevent the passage of charge, and b) said second voltage at a level to form a conduction path in the substrate beneath said third electrode means and for concurrently applying said first control voltage at a level to form a potential barrier in the substrate beneath said second electrode means.

Claim 4

An output circuit as set forth in claim 2, wherein said means for applying potentials comprises: means for concurrently applying a first voltage level to both of said first and second regions for operating both regions as sources of charge carriers and for then concurrently applying a second voltage level to both regions for operating them as drains for charge carriers; and signal output terminals at said respective regions.

Claim 5

An output circuit as set forth in claim 10, wherein said means for applying a first voltage level comprises means for concurrently supplying a packet of charge effectively of fixed size to said first region and a packet of charge effectively of fixed size to said second region.

Claim 6

In combination: a charge coupled device (CCD) delay line which includes a plurality of floating gates for producing a plurality of output signals in parallel; and a programmable output circuit, said output circuit comprising: first and second sense lines; a common substrate of given conductivity type; a plurality of stages, equal in number to the plurality of floating gates, each such stage coupled to a different floating gate, each such stage including: first electrode means coupled to a floating gate, said first electrode means being insulated from the substrate; first and second regions in said substrate of opposite conductivity type than the substrate, each spaced from said first electrode means, said first region coupled to said first sense line and said second region coupled to said second sense line; second and third electrode means, both insulated from said substrate and from said first electrode means, said second electrode means extending between said first region and said first electrode means for controlling in response to a single first control voltage whose level can be controlled, the conduction of charge between said first region and said first electrode means, and said second electrode means extending between said second region and said first electrode means for controlling in response to a single second control voltage whose level can be controlled, the flow of charge between said second region and said first electrode means; and program control means for supplying said first control voltage to the second electrode means of selected of said stages at a first level to create a conduction path between the first region and first electrode means of these stages, and for supplying said second control voltage to the third electrode means of said selected stages at a second level to create a potential barrier between the second region and first electrode means of said selected stages, and for supplying to the second and third electrode means of the remaining stages, said first control voltage at said second level and said second control voltage at said first level, respectively.

Claim 7

In combination: a charge coupled device (CCD) delay line which includes a plurality of floating gates for producing a plurality of output signals in parallel; and a programmable output circuit, said output circuit comprising: first and second sense lines; a common substrate of given conductivity type; a plurality of stages, equal in number to the plurality of floating gates, each such stage coupled to a different floating gate, each such stage including: first electrode means coupled to a floating gate, said first electrode means being insulated from the substrate; first and second regions in said substrate of opposite conductivity type than the substrate, each spaced from said first electrode means, said first region coupled to said first sense line and said second region coupled to said second sense line; second and third electrode means, both insulated from said substrate and from said first electrode means, said second electrode means extending between said first region and said first electrode means for controlling in response to a single first control voltage whose level can be controlled, the conduction of charge between said first region and said first electrode means, and said second electrode means extending between said second region and said first electrode means for controlling in response to a single second control voltage whose level can be controlled, the flow of charge between said second region and said first electrode means; and program control means for supplying said first control voltage to the second electrode means of selected of said stages at a first level to create a conduction path between the first region and first electrode means of these stages, and for supplying said second control voltage to the third electrode means of said selected stages at a second level to create a potential barrier between the second region and first electrode means of said selected stages, and for supplying to the second and third electrode means of the remaining stages, said first control voltage at said second level and said second control voltage at said first level, respectively.

Claim 8

In the combination as set forth in claim 5, further including: means for supplying packets of charge essentially of fixed size to said first and second lines, respectively, during each readout period, that is, during a period of time when charge is present beneath said floating gates.

Claim 9

In the combination as set forth in claim 6, further including: means operative after said packets of charge have been supplied to said first and second lines and still during each readout period, for changing the potential on said first and second lines to cause all first and second regions to operate as drains; and means for sensing the current flowing in each said line when said first and second regions are operating as drains.

Claim 10

In combination: a charge coupled device (CCD) delay line which includes a plurality of floating gates for producing a plurality of output signals in parallel; and a programmable output circuit, said output circuit comprising: first and second sense lines; a common substrate of given conductivity type; a plurality of stages, equal in number to the plurality of floating gates, each such stage coupled to a different floating gate, each such stage including: first electrode means coupled to a floating gate, said first electrode means being installed from the substrate; first and second regions in said substrate of opposite conductivity type than the substrate, each spaced from said first electrode means, said first region coupled to said first sense line and said second region coupled to said second sense line; second and third electrode means, both insulated from said substrate and from said first electrode means, said second electrode means extending between said first region and said first electrode means for controlling in response to a single first control voltage whose level can be controlled, the conduction of charge between said first region and said first electrode means, and said second electrode means extending between said second region and said first electrode means for controlling in response to a single second control voltage whose level can be controlled, the flow of charge between said second region and said first electrode means; and means for applying potentials to said first and second regions for permitting each to operate as a source of charge carriers for said substrate region beneath said first electrode means, the passage of such charge carriers being under the control of said second and third electrode means, respectively, and for applying potentials to said first and second regions for permitting each to operate as a drain for charge carriers from the substrate region beneath said first electrode means, the passage of such charge carriers being under the control of said second and third electrode means, respectively.

Claim 11

In combination: a charge coupled device (CCD) delay line which includes a plurality of floating gates for producing a plurality of output signals in parallel; and a programmable output circuit, said output circuit comprising: first and second sense lines; a common substrate of given conductivity type; a plurality of stages, equal in number to the plurality of floating gates, each such stage coupled to a different floating gate, each such stage including: first electrode means coupled to a floating gate, said first electrode means being installed from the substrate; first and second regions in said substrate of opposite conductivity type than the substrate, each spaced from said first electrode means, said first region coupled to said first sense line and said second region coupled to said second sense line; second and third electrode means, both insulated from said substrate and from said first electrode means, said second electrode means extending between said first region and said first electrode means for controlling in response to a single first control voltage whose level can be controlled, the conduction of charge between said first region and said first electrode means, and said second electrode means extending between said second region and said first electrode means for controlling in response to a single second control voltage whose level can be controlled, the flow of charge between said second region and said first electrode means; and means for applying potentials to said first and second regions for permitting each to operate as a source of charge carriers for said substrate region beneath said first electrode means, the passage of such charge carriers being under the control of said second and third electrode means, respectively, and for applying potentials to said first and second regions for permitting each to operate as a drain for charge carriers from the substrate region beneath said first electrode means, the passage of such charge carriers being under the control of said second and third electrode means, respectively.