US4612627A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital signal composing circuit for cross-fade signal processing
Assignee: Sony Corp
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Filing: 1983-12-13
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Granted: 1986-09-16
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Expires: 2003-12-13
Abstract
Abstract A digital signal composing circuit includes a first selector for selecting a plurality of digital data, a second selector for selecting one of the digital data and a feedback signal, a control circuit for controlling the switching of the first and second selectors and an adding circuit for adding outputs of the first and second selectors and supplying the added output to the second selector as the feedback signal wherein the final output is derived from the adding circuit. Thus, without using any multiplier, the signal processing can be widely used in the digital signal processing such as digital volume, cross-fade, fade-in/-out, mixing, linear interpolation and the like.
Inventors
- 👤 Takehiro Sugita
- 👤 Akira Sakamoto
- 👤 Takeshi Fukami
- 👤 Michimasa Komatsubara
- 👤 Akira Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:55
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10527; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G11B27/00; G11B27/02; G11B27/031; G11B27/038; H; H04; H04K; H04K1/00; H04K1/06
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
144 words
A digital cross-fader circuit for cross-fading from a first digital signal to a second digital signal, comprising: first selecting means responsive to a first control signal for supplying either of said first and second digital signals as a first selected signal; second selecting means responsive to a second control signal for supplying one of said first digital signal and a summed signal as a second selected signal; adding means for receiving said first and second selected signals and for adding one-half of said first selected signal and one-half of said second selected signal to produce said summed signal; signal output means for supplying an output signal in response to said summed signal; and controller means for producing said first and second control signals so that said output signal from said signal output means cross-fades from said first digital signal to said second digital signal.
Claim 2
Dependent Claim
144 words
A digital cross-fader circuit for cross-fading from a first digital signal to a second digital signal, comprising: first selecting means responsive to a first control signal for supplying either of said first and second digital signals as a first selected signal; second selecting means responsive to a second control signal for supplying one of said first digital signal and a summed signal as a second selected signal; adding means for receiving said first and second selected signals and for adding one-half of said first selected signal and one-half of said second selected signal to produce said summed signal; signal output means for supplying an output signal in response to said summed signal; and controller means for producing said first and second control signals so that said output signal from said signal output means cross-fades from said first digital signal to said second digital signal.
Claim 3
Dependent Claim
22 words
The circuit of claim 1; wherein said adding means includes latch means for supplying said summed signal to said second selecting means.
Claim 4
Dependent Claim
188 words
A digital cross-fader circuit for cross-fading from a first digital signal to a second digital signal, comprising: first selecting means responsive to a first control signal for supplying either of said first and second digital signals as a first selected signal; second selecting means responsive to a second control signal for supplying one of said first digital signal and a summed signal as a second selected signal; adding means for receiving said first and second selected signals and for adding one-half of said first selected signal and one-half of said selected signal to produce said summed signal; signal output means for supplying an output signal in response to said summed signal; and controller means for producing said first and second control signals so that said output signal from said signal output means cross-fades from said first digital signal to said second digital signal; wherein said adding means includes latch means for supplying said summed signal to said second selecting means; and wherein said controller means includes binary counter means for fading out said first digital signal and fading in said second digital signal over a predetermined cross-fade interval.
Claim 5
Dependent Claim
188 words
A digital cross-fader circuit for cross-fading from a first digital signal to a second digital signal, comprising: first selecting means responsive to a first control signal for supplying either of said first and second digital signals as a first selected signal; second selecting means responsive to a second control signal for supplying one of said first digital signal and a summed signal as a second selected signal; adding means for receiving said first and second selected signals and for adding one-half of said first selected signal and one-half of said selected signal to produce said summed signal; signal output means for supplying an output signal in response to said summed signal; and controller means for producing said first and second control signals so that said output signal from said signal output means cross-fades from said first digital signal to said second digital signal; wherein said adding means includes latch means for supplying said summed signal to said second selecting means; and wherein said controller means includes binary counter means for fading out said first digital signal and fading in said second digital signal over a predetermined cross-fade interval.
Claim 6
Dependent Claim
43 words
The circuit of claim 3; wherein said controller means includes switching circuit means for selectively supplying said first control signal to said first selecting means in response to a switching information signal; and second binary counter means for generating said switching information signal.
Claim 7
Dependent Claim
22 words
The circuit of claim 3; wherein said controller means includes means for generating said second control signal for said second selecting means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-15 | 1990-03-17 | 1990-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-15 | 1994-03-17 | 1994-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-15 | 1998-03-17 | 1998-09-16 | $7700.00 | Window Closed / Lapsed |