Multiplier for multiplying n-bit number by quotient of an integer divided by an integer power of two

Claim 1

A digital multiplier for multiplying together first and second numbers, when the first number is the quotient of an integer divided by an integer power of two and the second number has n bits, the multiplier comprising: a first n-bit register coupled to receive said second number; a second register having n+1 bits, said second register being coupled to said first for receiving said second number in the n least significant stages of said second register for effectively dividing the value of said second number by two to form a third number; a third register having n+2 bits coupled to said second register for receiving said third number in the n+1 least significant stages of said third register for effectively dividing the value of said third number by two to form a fourth number; a fourth register coupled for receiving the numerator of said first number, said fourth register having at least two stages for representing at least a portion of the value of said numerator in the form of one of two preassigned states which may be assumed by said stages, summing means; and coupling means coupled to said first and second stages of said fourth register, to said second and third registers and to said summing means for enabling said summing means for controllably forming an output signal from the values of one of said third, said fourth and the sum of said third and said fourth numbers.