US4368433A
Expired / Lapsed
US
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Signal converter circuit
Assignee: Fanuc Corp
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Filing: 1980-08-08
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Granted: 1983-01-11
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Expires: 2000-08-08
Abstract
Abstract An input signal is written in n memory elements one after another in accordance with clock pulses, the contents of the n memory elements are added together by an adder, and the added output from the adder is divided by n in a divider, thereby converting an input signal having an abrupt change to a signal having a gentle change.
Inventors
- 👤 Ryoji Imazeki
- 👤 Etsuo Yamazaki
- 👤 Takao Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:29
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/416; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G05B2219/00; G05B2219/30; G05B2219/43; G05B2219/43048
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
83 words
A signal converter circuit for receiving clock pulses and for converting an input signal, comprising: n memory elements for sequentially having the input signal written therein in synchrony with the clock pulses, wherein n is an integer greater than 1; an adder, operatively connected to said n memory elements, for adding together the contents of said n memory elements and for providing, as an output, an added result; and a divider, operatively connected to said adder, for dividing the added result by n.
Claim 2
Dependent Claim
83 words
A signal converter circuit for receiving clock pulses and for converting an input signal, comprising: n memory elements for sequentially having the input signal written therein in synchrony with the clock pulses, wherein n is an integer greater than 1; an adder, operatively connected to said n memory elements, for adding together the contents of said n memory elements and for providing, as an output, an added result; and a divider, operatively connected to said adder, for dividing the added result by n.
Claim 3
Dependent Claim
20 words
A signal converter circuit according to claim 1, wherein said n memory elements are cascade-connected to form a shift register.
Claim 4
Dependent Claim
34 words
A signal converter circuit according to claim 1, further comprising a scanner, operatively connected to said n memory elements, for scanning the input signal to write the input signal into said n memory elements.
Claim 5
Dependent Claim
111 words
A signal converter circuit comprising: means for receiving an analog input signal; an n-stage analog delay circuit, connected to said means for receiving said analog input signal, for sequentially shifting said analog input signal along said n stages of said analog delay circuit at a constant rate, where n is an integer greater than 1; an analog adder, connected to each stage of said analog delay circuit, for adding together the respective values held in each said stage of said analog delay circuit repeatedly in synchrony with said constant rate and for generating an added output; and a divider, connected to said analog adder, for dividing the added output by n.
Claim 6
Dependent Claim
111 words
A signal converter circuit comprising: means for receiving an analog input signal; an n-stage analog delay circuit, connected to said means for receiving said analog input signal, for sequentially shifting said analog input signal along said n stages of said analog delay circuit at a constant rate, where n is an integer greater than 1; an analog adder, connected to each stage of said analog delay circuit, for adding together the respective values held in each said stage of said analog delay circuit repeatedly in synchrony with said constant rate and for generating an added output; and a divider, connected to said analog adder, for dividing the added output by n.
Claim 7
Dependent Claim
101 words
A signal converter circuit comprising: means for receiving a digital input signal; means for receiving a clock signal; an n-stage shift register, connected to said digital input signal receiving means and said clock signal receiving means, for shifting said digital input signal synchronously with said clock signal, where n is an integer greater than 1; an adder, connected to each said stage of said n-stage shift register, for adding together the respective values held in each stage of said shift register and for generating an added output; and a divider, connected to said adder, for dividing the added output by n.
Claim 8
Dependent Claim
101 words
A signal converter circuit comprising: means for receiving a digital input signal; means for receiving a clock signal; an n-stage shift register, connected to said digital input signal receiving means and said clock signal receiving means, for shifting said digital input signal synchronously with said clock signal, where n is an integer greater than 1; an adder, connected to each said stage of said n-stage shift register, for adding together the respective values held in each stage of said shift register and for generating an added output; and a divider, connected to said adder, for dividing the added output by n.
Claim 9
Dependent Claim
45 words
The converter of claim 5, wherein n is an integral power of 2, and wherein said adder and divider are combined, said combined divider and adder both adding said respective stage values together and shifting the added value by k bits, where n=2 k .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-01-10 | 1986-07-12 | 1987-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-01-10 | 1990-07-12 | 1991-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-01-10 | 1994-07-12 | 1995-01-11 | $7700.00 | Window Closed / Lapsed |