US3983493A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital symmetric waveform synthesizer
Assignee: Verizon Laboratories Inc
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Filing: 1975-06-27
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Granted: 1976-09-28
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Expires: 1995-06-27
Abstract
Abstract A waveform synthesizer for generating analog waveforms is provided utilizing all MOSFET integrated circuit logic. The synthesizer includes an n stage clocked shift register in which the input to the first shift register stage is the inverted output of the last shift register stage. The output of each stage controls the state of a preselected weighting unit field effect transistor which provides a preselected output whenever the corresponding shift register stage is a logic 1. The outputs of all the weighting unit transistors are summed and applied to a summing field effect transistor.
Inventors
- 👤 Jerry M. Gladstone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:29
CPC Classifications
H; H03; H03K; H03K4/00; H03K4/02; H03K4/026
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
180 words
A digital generator for producing an analog waveform including: a. an n stage clocked shift register having an inverter coupled between the output of the nth stage and the input of the first stage, the logic state of any stage being shifted to an adjacent stage in the direction from the first stage to the nth stage at a rate related to the clock signal, b. means responsive to a first logic level of each shift register stage for generating up to n preselected weighted currents, and responsive to a second logic level of each shift register stage for generating no current, c. means for summing the preselected weighted currents to produce an analog voltage waveform whose shape is related to the sum of the preselected weighted output currents, and d. means responsive to the output of the nth stage for resetting each stage of the shift register to the second level when the nth stage changes from the first level to the second level to insure that each shift register stage at said change is at the second level.
Claim 2
Dependent Claim
180 words
A digital generator for producing an analog waveform including: a. an n stage clocked shift register having an inverter coupled between the output of the nth stage and the input of the first stage, the logic state of any stage being shifted to an adjacent stage in the direction from the first stage to the nth stage at a rate related to the clock signal, b. means responsive to a first logic level of each shift register stage for generating up to n preselected weighted currents, and responsive to a second logic level of each shift register stage for generating no current, c. means for summing the preselected weighted currents to produce an analog voltage waveform whose shape is related to the sum of the preselected weighted output currents, and d. means responsive to the output of the nth stage for resetting each stage of the shift register to the second level when the nth stage changes from the first level to the second level to insure that each shift register stage at said change is at the second level.
Claim 3
Dependent Claim
137 words
The generator according to claim 1 wherein the generating means associated with each shift register stage includes a first MOS field effect transistor whose gate is coupled to the output of the respective shift register stage to permit the preselected current flow therethrough when the output of the stage has the first logic level and to permit no current when the output of the stage has the second logic level and a second MOS field effect transistor having a gate and drain coupled to separate constant voltage sources and having its source coupled to one of the source and drain electrodes of the first transistor for providing the preselected current when the first transistor is conductive, the output of the generating means being taken from the other of the source and drain electrodes of the first transistor.
Claim 4
Dependent Claim
51 words
The generator according to claim 2 wherein the summing means includes an output conductor connecting the outputs of all of the first MOS field effect transistors and a summing field effect transistor for generating a voltage proportional to the sum of currents and further including means for filtering the output voltage.
Claim 5
Dependent Claim
36 words
The generator according to claim 3 wherein the second MOS field effect transistors are selected to provide symmetrical preselected currents with respect to the center of the shift register and further to provide a sinusoidal waveform.
Claim 6
Dependent Claim
14 words
The generator according to claim 4 wherein the first level is a logic 1.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-09-28 | 1980-03-29 | 1980-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-09-28 | 1984-03-29 | 1984-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-09-28 | 1988-03-29 | 1988-09-28 | $7700.00 | Window Closed / Lapsed |