Apparatus for analyzing microprocessor operation

Claim 2

Apparatus for analyzing an operation of a microprocessor including: a memory which stores various signals of said microprocessor in a system to be tested; an address counter which specifies an address of said memory; a setting condition input apparatus for inputting various setting conditions; a trigger comparator for comparing said various signals of said microprocessor and a trigger condition set previously, and for generating a coincident pulse (a trigger signal) when said various signals and said trigger condition are coincident; a memory control circuit for outputting a write pulse to said memory in response to a start signal and a clock pulse to said address counter, and for receiving said conincident pulse (trigger signal) from said trigger comparator, so as to stop said write pulse to said memory and the output of said clock pulse to said address counter; a display apparatus for displaying said various setting conditions input from said setting condition input apparatus and said various signals stored in said memory in a predetermined form; a control processor for outputting said various setting conditions from said setting condition input apparatus to said trigger comparator and to said display apparatus, and for outputting an address of said memory, and for reading desired data from said memory so as to output said data to said display apparatus, and for outputting said start signal to said memory control circuit; an address selection circuit for selecting an address to said memory from said control processor and an address to said memory from said address counter; and data switches connected to the input of said control process or for instructing a commencement of a data search operation.

Claim 3

Apparatus for analyzing an operation of a microprocessor comprising: a memory for storing signal conditions in a data bus, an address bus and a control bus of said microprocessor in a system to be tested; an address counter for generating an address of said memory; an address selection circuit for selecting an address to said memory for specifying the desired data and an address to said memory from said address counter, and for supplying the selected address to said memory; a setting condition input apparatus for inputting various setting conditions; a trigger comparator for comparing said signal conditions and trigger condition set previously, and for generating a conincident pulse (a trigger signal) when said signal conditions and said trigger condition are conincident; a memory control circuit for outputting a write pulse to said memory, an address selection signal to said address selection circuit and clock pulses to said address counter in response to a start signal and a control signal in the control signal in the control bus of the microprocessor, and which stops said write pulse, said address selection signal and said clock pulses when receiving said conincident pulse; a display apparatus for displaying said various setting conditions input from said setting condition input apparatus and said signal conditions in the data bus, the address bus and the control bus of said microprocessor; first switches for instructing a commencement of the data search operation; second switches for specifying an internal register of said microprocessor of the system to be tested; and a control processor for supplying said trigger condition to said trigger comparator by input from said set condition input apparatus, for supplying the start signal to said memory control circuit by the instruction of commencement from said first switches, and for supplying the address of said memory to said address selection circuit by the instruction from said second switches, and for automatically searching, from the data stored in said memory, the data when the microprocessor of the system to be tested executes an instruction by which the specified internal registers are changed, and for outputting the searched data to said display apparatus.

Claim 4

Apparatus for analyzing an operation of a microprocessor comprising: a memory for storing signal conditions in a data bus, an address bus and a control bus of said microprocessor in a system to be tested; an address counter for generating an address of said memory; an address selection circuit for selecting an address to said memory for specifying the desired data and an address to said memory from said address counter, and for supplying the selected address to said memory; a setting condition input apparatus for inputting various setting conditions; a trigger comparator for comparing said signal conditions and trigger condition set previously, and for generating a conincident pulse (a trigger signal) when said signal conditions and said trigger condition are conincident; a memory control circuit for outputting a write pulse to said memory, an address selection signal to said address selection circuit and clock pulses to said address counter in response to a start signal and a control signal in the control signal in the control bus of the microprocessor, and which stops said write pulse, said address selection signal and said clock pulses when receiving said conincident pulse; a display apparatus for displaying said various setting conditions input from said setting condition input apparatus and said signal conditions in the data bus, the address bus and the control bus of said microprocessor; first switches for instructing a commencement of the data search operation; second switches for specifying an internal register of said microprocessor of the system to be tested; and a control processor for supplying said trigger condition to said trigger comparator by input from said set condition input apparatus, for supplying the start signal to said memory control circuit by the instruction of commencement from said first switches, and for supplying the address of said memory to said address selection circuit by the instruction from said second switches, and for automatically searching, from the data stored in said memory, the data when the microprocessor of the system to be tested executes an instruction by which the specified internal registers are changed, and for outputting the searched data to said display apparatus.

Claim 5

Apparatus for analyzing an operation of a microprocessor comprising: a memory for storing signal condition in a data bus, an address bus and a control bus of said microprocessor system to be tested; an address counter for generating an address of said memory; an address selection circuit for selecting an address to said memory for specifying the desired data and an address to said memory from said address counter, and for supplying the selected address to said memory; a setting condition input apparatus for inputting various setting conditions; a trigger comparator for comparing said signal conditions and trigger condition set previously, and for generating a coincident pulse (a trigger signal) when said signal conditions and said trigger condition are coincident; a memory control circuit for outputting a write pulse to said memory, an address selection signal to said address selection circuit and clock pulses to said address counter in response to a start signal and a control signal in the control signal in the control bus of the microprocessor, and which stops said write pulse, said address selection signal and said clock pulses when receiving said coincident pulse; a display apparatus for displaying said various setting conditions input from said setting condition input apparatus and said signal conditions in the data bus, the address bus and the control bus of said microprocessor; switches for instructing a commencement of the data search operation; a control processsor for supplying said trigger condition to said trigger comparator by input from said set condition input apparatus, for supplying the start signal to said memory control circuit by the instruction of commencement from said switches, and for supplying the address of said memory to said address selection circuit and for outputting the searched data to said display apparatus.

Claim 6

Apparatus for analyzing an operation of a microprocessor comprising: a memory for storing signal condition in a data bus, an address bus and a control bus of said microprocessor system to be tested; an address counter for generating an address of said memory; an address selection circuit for selecting an address to said memory for specifying the desired data and an address to said memory from said address counter, and for supplying the selected address to said memory; a setting condition input apparatus for inputting various setting conditions; a trigger comparator for comparing said signal conditions and trigger condition set previously, and for generating a coincident pulse (a trigger signal) when said signal conditions and said trigger condition are coincident; a memory control circuit for outputting a write pulse to said memory, an address selection signal to said address selection circuit and clock pulses to said address counter in response to a start signal and a control signal in the control signal in the control bus of the microprocessor, and which stops said write pulse, said address selection signal and said clock pulses when receiving said coincident pulse; a display apparatus for displaying said various setting conditions input from said setting condition input apparatus and said signal conditions in the data bus, the address bus and the control bus of said microprocessor; switches for instructing a commencement of the data search operation; a control processsor for supplying said trigger condition to said trigger comparator by input from said set condition input apparatus, for supplying the start signal to said memory control circuit by the instruction of commencement from said switches, and for supplying the address of said memory to said address selection circuit and for outputting the searched data to said display apparatus.