Patent US4609830A successfully refreshed from Google Patents.
US4609830A
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Programmable logic gate
Assignee: Zoran Corp
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Filing: 1983-11-28
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Granted: 1986-09-02
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Expires: 2003-11-28
Abstract
Abstract A programmable logic gate includes first and second complementary field effect transistors having gate terminals connected to receive a first input signal. A first variable resistance is connected in series with the first transistor, and a second variable resistance is connected in parallel with the second transistor. The variable resistances can be fusible links or variable resistance semiconductor devices. By increasing the resistance of the first variable resistance and decreasing the resistance of the second variable resistance, the input signal becomes ineffective in the logic gate. Conversely, by decreasing the resistance of the first variable resistance and increasing the resistance of the second variable resistance, the input signal becomes effective in operation of the logic circuit. In programming the transistors, one transistor is effectively disconnected from the gate and the complementary transistor is effectively shorted.
Inventors
- 👤 Yigal Brandman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 04:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
265 words
A logic gate comprising a first P channel field effect transistor and a first variable resistance device connected in parallel, a second P channel field effect transistor and a second variable resistance device connected in parallel, a third N channel field effect transistor and a third variable resistance device serially connected, a fourth N channel field effect transistor and a fourth variable resistance device serially connected, means connecting the series connection of said third field effect transistor and third variable resistance device in parallel with the series connection of said fourth field effect transistor and said fourth variable resistance device thereby forming parallel circuitry, means serially connecting the parallel connection of said first field effect transistor and first variable resistance device, the parallel connecting of said second field effect transistor and second variable resistance device, and said parallel circuitry between first and second voltage potentials, means for applying a first input to said first and third field effect transistors, means for applying a second input to said second and fourth field effect transistors, means for obtaining an output at the connection between the parallel connection of said second field effect transistor with said second variable resistance device and said parallel circuitry in response to said first and second inputs, said first, second, third, and fourth variable resistance devices having a high resistance state and a low resistance state for selectively enabling said first input and said second input, and means for selectively applying sufficient current through said first, second, third, and fourth variable resistance devices to thereby alter the resistances of said variable resistance devices.
Claim 2
Dependent Claim
265 words
A logic gate comprising a first P channel field effect transistor and a first variable resistance device connected in parallel, a second P channel field effect transistor and a second variable resistance device connected in parallel, a third N channel field effect transistor and a third variable resistance device serially connected, a fourth N channel field effect transistor and a fourth variable resistance device serially connected, means connecting the series connection of said third field effect transistor and third variable resistance device in parallel with the series connection of said fourth field effect transistor and said fourth variable resistance device thereby forming parallel circuitry, means serially connecting the parallel connection of said first field effect transistor and first variable resistance device, the parallel connecting of said second field effect transistor and second variable resistance device, and said parallel circuitry between first and second voltage potentials, means for applying a first input to said first and third field effect transistors, means for applying a second input to said second and fourth field effect transistors, means for obtaining an output at the connection between the parallel connection of said second field effect transistor with said second variable resistance device and said parallel circuitry in response to said first and second inputs, said first, second, third, and fourth variable resistance devices having a high resistance state and a low resistance state for selectively enabling said first input and said second input, and means for selectively applying sufficient current through said first, second, third, and fourth variable resistance devices to thereby alter the resistances of said variable resistance devices.
Claim 3
Dependent Claim
15 words
The logic gate as defined by claim 1 wherein said resistance devices comprise fusible links.
Claim 4
Dependent Claim
17 words
The logic gate as defined by claim 1 wherein said resistance devices comprise doped polycrystalline semiconductor material.
Claim 5
Dependent Claim
269 words
A logic gate comprising a first P channel field effect transistor and a first variable resistance device connected in series, a second P channel field effect transistor and a second variable resistance device connected in series, a third N channel field effect transistor and a third variable resistance device serially connected in parallel, a fourth N channel field effect transistor and a fourth variable resistance device connected in parallel, means connecting the series connection of said first field effect transistor and said first variable resistance device in parallel with the series connection of said second field effect transistor and said second variable resistance device thereby forming parallel circuitry, means serially connecting the parallel connection of said third field effect transistor and third variable resistance device, the parallel connection of said fourth field effect transistor and fourth variable resistance device, and said parallel circuitry between first and second voltage potentials, means for applying a first input to said first and third field effect transistors, means for applying a second input to said second and fourth field effect transistors, means for obtaining an output at the connection between the parallel connection of said third field effect transistor with the third variable resistance device and said parallel circuitry in response to said first and second inputs, said first, second, third, and fourth variable resistance devices having a high resistance state and a low resistance state for selectively enabling said first input and said second input, and means for selectively applying sufficient current through said first, second, third, and fourth variable resistance devices to thereby alter the resistance of said variable resistance devices.
Claim 6
Dependent Claim
269 words
A logic gate comprising a first P channel field effect transistor and a first variable resistance device connected in series, a second P channel field effect transistor and a second variable resistance device connected in series, a third N channel field effect transistor and a third variable resistance device serially connected in parallel, a fourth N channel field effect transistor and a fourth variable resistance device connected in parallel, means connecting the series connection of said first field effect transistor and said first variable resistance device in parallel with the series connection of said second field effect transistor and said second variable resistance device thereby forming parallel circuitry, means serially connecting the parallel connection of said third field effect transistor and third variable resistance device, the parallel connection of said fourth field effect transistor and fourth variable resistance device, and said parallel circuitry between first and second voltage potentials, means for applying a first input to said first and third field effect transistors, means for applying a second input to said second and fourth field effect transistors, means for obtaining an output at the connection between the parallel connection of said third field effect transistor with the third variable resistance device and said parallel circuitry in response to said first and second inputs, said first, second, third, and fourth variable resistance devices having a high resistance state and a low resistance state for selectively enabling said first input and said second input, and means for selectively applying sufficient current through said first, second, third, and fourth variable resistance devices to thereby alter the resistance of said variable resistance devices.
Claim 7
Dependent Claim
15 words
The logic gate as defined by claim 4 wherein said resistance devices comprise fusible links.
Claim 8
Dependent Claim
17 words
The logic gate as defined by claim 4 wherein said resistance devices comprise doped polycrystalline semiconductor material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-01 | 1990-03-03 | 1990-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-01 | 1994-03-03 | 1994-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-01 | 1998-03-03 | 1998-09-02 | $7700.00 | Window Closed / Lapsed |