Patent US4604536A successfully refreshed from Google Patents.
US4604536A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timing circuits
Assignee: EMI Ltd
•
Filing: 1984-03-08
•
Granted: 1986-08-05
•
Expires: 2004-03-08
Abstract
Abstract A clock circuit is initiated by an external trigger pulse. Timing measurements commence at a first rate, and after a first delay (t 1 ) which is sufficient to allow an oscillator of the clock circuit to stabilize. After a second delay (t 1 ) the clock circuit operates at a second rate which is half the first rate. The clock circuit then represents the time from reception of the external trigger pulse. The first and second delays are derived by charging a capacitor at a constant rate and comparing the voltage level developed across it with respective reference voltages (V 1 , V 2 ) in comparators. In general, the second rate may be 1/r+1 times the first rate, where r is the ratio of the first delay to the second delay.
Inventors
- 👤 Richard C. D. Clutterbuck
- 👤 Anthony R. Painton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:18
CPC Classifications
G; G04; G04F; G04F10/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
141 words
A timing circuit comprising, a control circuit including a first pulse generating means for generating a first control pulse on expiry of a first delay, of preset duration, measured from reception of an external pulse, and a second pulse generating means for generating a second control pulse on expiry of a second delay, of preset duration, measured from the end of said first delay; and a clock circuit including means for generating clock pulses and counting means, responsive to said first and second control pulses, to count said clock pulses respectively at a first rate and a second rate, 1/(r+1) times the first rate, where r is the ratio of said first delay to said second delay, whereby after said second delay the count produced by said counting circuit represents the elapsed time as measured from reception of said external pulse.
Claim 2
Dependent Claim
141 words
A timing circuit comprising, a control circuit including a first pulse generating means for generating a first control pulse on expiry of a first delay, of preset duration, measured from reception of an external pulse, and a second pulse generating means for generating a second control pulse on expiry of a second delay, of preset duration, measured from the end of said first delay; and a clock circuit including means for generating clock pulses and counting means, responsive to said first and second control pulses, to count said clock pulses respectively at a first rate and a second rate, 1/(r+1) times the first rate, where r is the ratio of said first delay to said second delay, whereby after said second delay the count produced by said counting circuit represents the elapsed time as measured from reception of said external pulse.
Claim 3
Dependent Claim
63 words
A timing circuit according to claim 1 wherein said control circuit comprises a voltage source for generating a linearly increasing voltage in response to said external pulse, and wherein said first and second pulse generating means comprises respective comparison means for generating said first and second control pulses when the voltage generated by said voltage source respectively attains first and second reference levels.
Claim 4
Dependent Claim
27 words
A timing circuit according to claim 2 wherein said voltage source comprises a constant current source arranged to charge a capacitor in response to said external pulse.
Claim 5
Dependent Claim
37 words
A timing circuit according to claim 3 wherein one input of each said comparison means is connected electrically to sense the voltage across said capacitor and the other input is connected electrically to a respective reference voltage.
Claim 6
Dependent Claim
18 words
A timing circuit according to claim 1 wherein r has a value in the range 0.1 to 2.0.
Claim 7
Dependent Claim
17 words
A timing circuit according to claim 2 wherein r has the value 1, 3, 7 or 15.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-04 | 1990-02-03 | 1990-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-04 | 1994-02-03 | 1994-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-04 | 1998-02-03 | 1998-08-05 | $7700.00 | Window Closed / Lapsed |