US3906374A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Symmetrical odd-modulus frequency divider
Assignee: National Aeronautics and Space Administration
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Filing: 1974-03-12
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Granted: 1975-09-16
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Expires: 1994-03-12
Abstract
Abstract A frequency divider arrangement that can be used for division by an odd number and which provides a symmetrical output. It comprises an exclusive Or gate followed by a divide by 2N counter where (2N-1) equals the odd number. Input to the exclusive Or gate is from a pulse source and from the counter output.
Inventors
- 👤 James C Administrator Fletcher
- 👤 Alexander Engel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:45
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/70; H03K21/00; H03K21/08
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
113 words
A system for dividing the signals from a symmetrical frequency source by an odd-modulus and achieving a symmetrical output comprising a counter having an input and an output indicative of its 2N count state, where N equals the odd-modulus division desired plus one divided by two, and gate means for applying either output signals from said symmetrical frequency source or the 2N count state output of said counter to said counter input to be counted whereby the frequency of the full count state output of said counter is an odd-modulus of the frequency of said symmetrical frequency source and said counter produces a symmetrical waveform output in response to each 2N input pulses.
Claim 2
Independent Claim
113 words
A system for dividing the signals from a symmetrical frequency source by an odd-modulus and achieving a symmetrical output comprising a counter having an input and an output indicative of its 2N count state, where N equals the odd-modulus division desired plus one divided by two, and gate means for applying either output signals from said symmetrical frequency source or the 2N count state output of said counter to said counter input to be counted whereby the frequency of the full count state output of said counter is an odd-modulus of the frequency of said symmetrical frequency source and said counter produces a symmetrical waveform output in response to each 2N input pulses.
Claim 3
Dependent Claim
16 words
A system as recited in claim 1 wherein said gate means is an exclusive OR gate.
Claim 4
Dependent Claim
18 words
A system as recited in claim 1 wherein said counter counts only in response to positive-going signal wavefronts.
Claim 5
Dependent Claim
18 words
A system as recited in claim 1 wherein said counter counts only in response to negative-going signal wavefronts.
Claim 6
Independent Claim
130 words
A system for dividing the signals from a symmetrical frequency source by an odd-modulus and achieving a symmetrical output comprising an exclusive OR gate having a first and second input and an output, a counter having an input and a 2N count output, where N equals the odd-modulus division desired plus one divided by two, means to apply signals from the source of signals to the first input to said exclusive OR gate, means to apply the 2N count output of said counter to said exclusive OR gate''s second input, means to apply the output of said exclusive OR gate to said counter to be counted, and means to derive a symmetrical waveform output of said counter in response to 2N input pulses to said OR gate from said source.
Claim 7
Independent Claim
130 words
A system for dividing the signals from a symmetrical frequency source by an odd-modulus and achieving a symmetrical output comprising an exclusive OR gate having a first and second input and an output, a counter having an input and a 2N count output, where N equals the odd-modulus division desired plus one divided by two, means to apply signals from the source of signals to the first input to said exclusive OR gate, means to apply the 2N count output of said counter to said exclusive OR gate''s second input, means to apply the output of said exclusive OR gate to said counter to be counted, and means to derive a symmetrical waveform output of said counter in response to 2N input pulses to said OR gate from said source.
Claim 8
Dependent Claim
24 words
A system as recited in claim 5 wherein said 2N count output of said counter comprises the full count state output of said counter.
References Cited (Backward Citations)
US3328702A
Cited
US3721904A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |