US4602419A
Expired / Lapsed
US
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Method of making junction field effect transistor
Assignee: QED Intellectual Property Ltd
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Filing: 1984-01-09
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Granted: 1986-07-29
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Expires: 2004-01-09
Abstract
Abstract A junction field effect transistor has a substrate forming a junction with a layer of semiconductor material which has a gate, a source and a drain therein. The thickness of the n-type layer underlying the source is substantially greater than that underlying the gate (for example the ratio of n-thickness below the gate to that below the source is 1 to 2.53) in order to reduce the parasitic resistance as compared to conventional JFETs.
Inventors
- 👤 Alan J. Harrison
- 👤 Tawfic S. Nashashibi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:56
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83; Y; Y10; Y10S; Y10S438/00; Y10S438/965
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
220 words
A method of manufacturing junction field effect transistors comprising: depositing a first layer of semiconductor material on a substrate of semiconductor material to produce a junction; forming an anti-oxidation layer over the first layer, the anti-oxidation layer having a plurality of first windows which expose portions of the first layer; effecting diffusion of the layered substrate under oxidation conditions; removing a plurality of sections of the anti-oxidation layer to produce second windows in the anti-oxidation layer such as to expose further portions of the first layer; effecting diffusion of the resultant layered substrate under oxidation conditions, whereby enhanced diffusion occurs in the material underlying the first windows and the second windows, to such a degree whereby the first layer is fragmented into distinct divisions separated by diffused semiconductor material corresponding to that of the first layer and underlying the first windows but not the second windows, a such division of the first layer having a region of reduced thickness underlying the second window corresponding to that division; forming, for each such division of the first layer, a gate in the vicinity of the appropriate second window and a source and drain elsewhere on the division; and then cutting up the layered substrate along lines constituted by the enhanced-diffusion material formed by the first windows, thereby to separate the said divisions.
Claim 2
Independent Claim
220 words
A method of manufacturing junction field effect transistors comprising: depositing a first layer of semiconductor material on a substrate of semiconductor material to produce a junction; forming an anti-oxidation layer over the first layer, the anti-oxidation layer having a plurality of first windows which expose portions of the first layer; effecting diffusion of the layered substrate under oxidation conditions; removing a plurality of sections of the anti-oxidation layer to produce second windows in the anti-oxidation layer such as to expose further portions of the first layer; effecting diffusion of the resultant layered substrate under oxidation conditions, whereby enhanced diffusion occurs in the material underlying the first windows and the second windows, to such a degree whereby the first layer is fragmented into distinct divisions separated by diffused semiconductor material corresponding to that of the first layer and underlying the first windows but not the second windows, a such division of the first layer having a region of reduced thickness underlying the second window corresponding to that division; forming, for each such division of the first layer, a gate in the vicinity of the appropriate second window and a source and drain elsewhere on the division; and then cutting up the layered substrate along lines constituted by the enhanced-diffusion material formed by the first windows, thereby to separate the said divisions.
Claim 3
Dependent Claim
50 words
A method according to claim 1, wherein the diffusion steps are of such duration as to produce, in a completed junction field effect transistor, a ratio of semiconductor layer thickness below the gate to that thickness below the source in the range between 1 to 1.75 and 1 to 3.5.
Claim 4
Dependent Claim
50 words
A method according to claim 1, wherein the diffusion steps are of such duration as to produce, in a completed junction field effect transistor, a ratio of semiconductor layer thickness below the gate to that thickness below the source in the range between 1 to 2 and 1 to 3.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-28 | 1990-01-27 | 1990-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-28 | 1994-01-27 | 1994-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-28 | 1998-01-27 | 1998-07-29 | $7700.00 | Window Closed / Lapsed |