US4599576A
Expired / Lapsed
US
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Insulated gate type field effect semiconductor device and a circuit employing the device
Assignee: Hitachi Ltd
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Filing: 1978-03-01
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Granted: 1986-07-08
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Expires: 1998-03-01
Abstract
Abstract An insulated gate type field effect transistor for high power which has a low conductivity region surrounding a drain region and an offset gate region having a further lower conductivity adjoined thereto, wherein the length and impurity concentration are designed according to the electric characteristics of the transistor. A combination of P channel and N channel type transistors having substantially the same electric characteristics and an audio amplifying circuit using the combination are also disclosed.
Inventors
- 👤 Isao Yoshida
- 👤 Takeaki Okabe
- 👤 Shikayuki Ochi
- 👤 Hidefumi Ito
- 👤 Masatomo Furumi
- 👤 Masaru Takeuchi
- 👤 Minoru Nagata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:27
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/30; H03F3/3001; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/603; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/8311; H10D84/835; H10D84/836; H10D84/85; H10D89/00; H10D89/60; H10D89/601; H10W; H10W72/00; H10W72/50; H10W72/531; H10W72/5363
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
159 words
Combination of a P channel type insulated gate type field effect transistor and an N channel type insulated gate type field effect transistor having substantially the same electric characteristics except for the polarity thereof, each transistor having a source and a drain region formed in a semiconductor body, a low doped offset gate region of the same conductivity type as said drain region formed in the major surface of the body between the source and drain regions adjacent to the drain region, an insulating film formed on the major surface of said body, and a gate electrode formed on said insulating film so as to cover the major surface lying between said source region and said offset gate region and defining a channel area of the transistor, wherein the length of said offset gate region and the channel width of said N channel type transistor are made respectively larger and smaller than that of said P channel type transistor.
Claim 2
Dependent Claim
159 words
Combination of a P channel type insulated gate type field effect transistor and an N channel type insulated gate type field effect transistor having substantially the same electric characteristics except for the polarity thereof, each transistor having a source and a drain region formed in a semiconductor body, a low doped offset gate region of the same conductivity type as said drain region formed in the major surface of the body between the source and drain regions adjacent to the drain region, an insulating film formed on the major surface of said body, and a gate electrode formed on said insulating film so as to cover the major surface lying between said source region and said offset gate region and defining a channel area of the transistor, wherein the length of said offset gate region and the channel width of said N channel type transistor are made respectively larger and smaller than that of said P channel type transistor.
Claim 3
Dependent Claim
29 words
The combination according to claim 1, wherein said body for said N channel type transistor has further a low resistivity semiconductor region lying under said source and drain regions.
Claim 4
Dependent Claim
33 words
The combination according to claim 1, wherein the length of said offset gate region of said N channel type transistor is 1.5 to 6.0 times greater than that of said P-channel type transistor.
Claim 5
Dependent Claim
30 words
The combination according to claim 1, wherein the channel length of said N channel type transistor is 1.1 to 1.5 times greater than that of said P channel type transistor.
Claim 6
Dependent Claim
54 words
The combination according to claim 1, wherein a number calculated by an expression W/Tox·Lc, wherein W, Tox and Lc are the channel width, channel length and thickness of the gate insulating film in the P channel type transistor, respectively, is 1.8 to 2.8 times greater than that calculated in the N channel type transistor.
Claim 7
Dependent Claim
177 words
A circuit comprising a P channel type insulated gate field effect transistor and an N channel type insulated gate field effect transistor, each transistor having a source and a drain region formed in a semiconductor body, a low doped offset gate region of the same conductivity type as said drain region, a source electrode connected to said source region, a drain electrode connected to said drain region, a gate electrode formed on an insulating film covering the major surface defining the channel of the transistor between said source region and said offst gate region, and a substrate electrode means provided to said body, connecting means for directly connecting said source electrodes and substrate electrodes of said both transistors in common to an output terminal, bias adjusting means connected to said gate electrodes of said transistors, and means for applying an input signal to the gate electrodes coupled to said gate electrodes, wherein said N channel type transistor has a length of said offset gate region longer and a channel width smaller than said P channel type transistor.
Claim 8
Dependent Claim
177 words
A circuit comprising a P channel type insulated gate field effect transistor and an N channel type insulated gate field effect transistor, each transistor having a source and a drain region formed in a semiconductor body, a low doped offset gate region of the same conductivity type as said drain region, a source electrode connected to said source region, a drain electrode connected to said drain region, a gate electrode formed on an insulating film covering the major surface defining the channel of the transistor between said source region and said offst gate region, and a substrate electrode means provided to said body, connecting means for directly connecting said source electrodes and substrate electrodes of said both transistors in common to an output terminal, bias adjusting means connected to said gate electrodes of said transistors, and means for applying an input signal to the gate electrodes coupled to said gate electrodes, wherein said N channel type transistor has a length of said offset gate region longer and a channel width smaller than said P channel type transistor.
Claim 9
Dependent Claim
125 words
An audio amplifier comprising a P channel type insulated gate field effect transistor and an N channel type insulated gate field effect transistor, each transistor having a source and a drain electrode and an insulated gate electrode, connecting means for connecting said source electrodes of both transistors in common to an output terminal, bias adjusting means connected to said gate electrodes of both transistors, means for supplying an input signal to said gate electrodes, and connecting means for connecting an audio speaker to said output terminal, wherein each said transistor has an offset gate region in a semiconductor body and said N channel type transistor has a length of said offset gate region longer and a channel width smaller than said P channel type transistor.
Claim 10
Dependent Claim
125 words
An audio amplifier comprising a P channel type insulated gate field effect transistor and an N channel type insulated gate field effect transistor, each transistor having a source and a drain electrode and an insulated gate electrode, connecting means for connecting said source electrodes of both transistors in common to an output terminal, bias adjusting means connected to said gate electrodes of both transistors, means for supplying an input signal to said gate electrodes, and connecting means for connecting an audio speaker to said output terminal, wherein each said transistor has an offset gate region in a semiconductor body and said N channel type transistor has a length of said offset gate region longer and a channel width smaller than said P channel type transistor.
Claim 11
Dependent Claim
24 words
The invention according to claim 1, 6 or 7, wherein said offset gate region is shallower in depth than said source and drain regions.
References Cited (Backward Citations)
US3440500A
Cited
FR2027452A1
Cited
US4005450A
Cited
US4092661A
Cited
US4021751A
Cited
US4057764A
Cited
US4058822A
Cited
US4079504A
Cited
US4154626A
Cited
US4172260A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-07 | 1990-01-06 | 1990-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-07 | 1994-01-06 | 1994-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-07 | 1998-01-06 | 1998-07-08 | $7700.00 | Window Closed / Lapsed |