US4092661A
Expired / Lapsed
US
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Mosfet transistor
Assignee: Intel Corp
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Filing: 1976-05-20
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Granted: 1978-05-30
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Expires: 1996-05-20
Abstract
Abstract An n channel MOSFET transistor which includes doping of previously formed source and drain elements with a heavy diffusion of phosphorous or arsenic creating n++ regions in the source and drain. The extra diffusion step is preferably accomplished just prior to contact metalization.
Inventors
- 👤 Willis G. Watrous, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:23
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D99/00; H10P; H10P95/00; H10W; H10W20/00; H10W20/40; Y; Y10; Y10S; Y10S148/00; Y10S148/04; Y10S148/06; Y10S148/133; Y10S148/167; Y10S438/00; Y10S438/978; Y10T; Y10T29/00; Y10T29/53; Y10T29/53909; Y10T29/53913
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
151 words
A field effect semiconductor device which comprises: (a) a p type semiconductor region; (b) a pair of spaced n type regions diffused into the surface of said p type region, said spaced n type regions forming the source and drain regions and defining a channel of said field effect semiconductor device; (c) at least one gate element insulated from said p type semiconductor region and located between and in a substantially nonoverlapping relationship with said spaced n type regions; (d) a pair of n++ type regions, formed by diffusion of an impurity, within the pair of said spaced n type regions and (e) pn junctions between each of said n type regions and said p type region, those portions of each said pn junction directly adjacent said channel being shallower, with respect to said surface, than deeper portions of said pn junctions, said deeper portions being more distal from said channel.
Claim 2
Dependent Claim
151 words
A field effect semiconductor device which comprises: (a) a p type semiconductor region; (b) a pair of spaced n type regions diffused into the surface of said p type region, said spaced n type regions forming the source and drain regions and defining a channel of said field effect semiconductor device; (c) at least one gate element insulated from said p type semiconductor region and located between and in a substantially nonoverlapping relationship with said spaced n type regions; (d) a pair of n++ type regions, formed by diffusion of an impurity, within the pair of said spaced n type regions and (e) pn junctions between each of said n type regions and said p type region, those portions of each said pn junction directly adjacent said channel being shallower, with respect to said surface, than deeper portions of said pn junctions, said deeper portions being more distal from said channel.
Claim 3
Dependent Claim
17 words
The device of claim 1 where impurity is selected from the group consisting of phosphorous and arsenic.
Claim 4
Dependent Claim
17 words
The device of claim 1 wherein said p type semiconductor region has a 100 plane crystal orientation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-05-29 | 1981-11-28 | 1982-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-05-29 | 1985-11-28 | 1986-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-05-29 | 1989-11-28 | 1990-05-30 | $7700.00 | Window Closed / Lapsed |