Circuit arrangement for frame and phase synchronization of a local sampling clock

Claim 1

An arrangement for synchronizing a local sampling clock to frame position and phase of the characters of a received character stream containing a unique word at regular time intervals, said arrangement including a digital correlator which generates a crosscorrelation function from the received character stream, sampled at a sampling clock rate, and a unique word stored in said correlator and comprising a first frame detection circuit which derives a first frame clock from those maxima of the crosscorrelation function recurring at intervals of one frame period, and a second frame detection circuit (3) which derives a second frame clock from those minima of the crosscorrelation function recurring at intervals of one frame period, the time of a first occurrence of a maximum or a minimum having a time index io, and further comprising a clock selection circuit (8) connected to said frame detection circuits which determines which of the two frame clocks is being received within a limited time interval, and comprising also a phase synchronization circuit (10) connected to said clock selection circuit, said phase synchronization circuit receiving control information related to the selected frame clock for providing phase information (ΔP) for control of the sampling clock (AT), said phase synchronization circuit also being coupled to said digital correlator whereby values of said crosscorrelation function are fed thereto and wherein the phase information (ΔP) is provided as a function of values K(i 0 +1), K(i 0 -1) which the crosscorrelation function has in the vicinity of the maximum or minimum.