Frame synchronization system

Claim 2

A frame synchronization system for a time division multiplex binary data station comprising: at least a first source of binary data signals including in each of repetitive predetermined length frame periods M time multiplexed groups of time multiplexed channel signals, each of said M groups including any one of m different sync signals, where M and m are integers greater than one; an input; first means coupled to said first source and said input to couple said M groups time sequentially to said input; second means to produce a first timing signal having a frequency equal to the bit rate of said binary data signals; m third means each having first and second inputs, said first input of each of said m third means being coupled to said input, each of said m third means responding to a different one of said m sync signals, each of said m third means examining successive bits in each of said M groups within each of said frame periods to determine the presence of its associated one of said m sync signals and to produce a phase control signal in the absence of its associated one of said m sync signals in a given number of successive bits; and m fourth means each coupled to the output of a different associated one of said m third means and between said second means and said second input of the associated one of said m third means responsive to the associated one of said control signals to control the phase of said first timing signal with respect to those of said M groups having the associated one of said m sync signals responsible for producing the associated one of said control signals to establish and maintain synchronization.

Claim 3

A system according to claim 1, wherein each of said third means includes a digital comparator coupled to said input, and an integrator having a search threshold coupled to the output of said comparator to produce said control signal.

Claim 4

A system according to claim 2, wherein said integrator includes an up-down binary counter having a search count threshold to produce said control signal.

Claim 5

A system according to claim 3, wherein at least one of said third means further includes a timing signal generator to produce a reference signal and second timing signal to define the time that said sync signals should occur and; the associated one of said comparators is coupled to said timing signal generator and said input to compare said reference signal with said successive bits; and at least one of said fourth means includes first logic circuitry coupled between said second means and said timing signal generator to normally couple said first timing signal to said timing signal generator, and second logic circuitry coupled to one of said third means, said timing signal generator, and said first logic circuitry responsive to said second timing signal and its associated one of said control signals when its associated one of said coUnters is below said count threshold to place said associated one of said control signals in a binary 1 condition to produce a signal for coupling to said first logic circuitry to halt the coupling of said first timing signal to said timing signal generator to enable said phase control.

Claim 6

A system according to claim 3, wherein at least one of said third means further includes a timing signal generator to produce a reference signal and second timing signal to define the time that said sync signals should occur; and the associated one of said comparators is coupled to said timing signal generator and said input to compare said reference signal with said successive bits; and at least one of said fourth means includes logic circuitry coupled between said second means and said timing signal generator to normally couple said first timing signal to said timing signal generator, a first AND gate coupled to said one of said third means and said timing signal generator responsive to said second timing signal and its associated one of said control signals when its associated one of said counters is below said count threshold to place said associated one of said control signals in a binary 1 condition to produce a search enable signal, storage means to store the results of a given number of previous comparisons of its associated one of said comparators, a two input OR gate having one input coupled to the output of said comparator of said one of said third means, the other input coupled to the output of said storage means and an output coupled to the input of said storage means, and a second AND gate coupled to said first AND gate and the output of said OR gate responsive to a binary 1 output of said OR gate and said search enable signal to produce a signal for coupling to said logic circuitry to halt the coupling of said first timing signal to said timing signal generator to enable said phase control.

Claim 7

A system according to claim 3, wherein at least one of said comparators includes a shift register coupled to said input to store said binary data signals at said bit rate, and first logic circuitry coupled to said shift register and the input of the associated one of said counters to examine said successive bits at said bit rate to determine the presence and absence of the associated one of said m sync signals.

Claim 8

A system according to claim 6, wherein said fourth means associated with said one of said comparators further includes second logic circuitry coupled between said second means and said shift register and between said second means and said first logic circuitry to normally couple said first timing signal to said shift register and said first logic circuitry, and third logic circuitry coupled to the associated one of said counters, said second means and said second logic circuitry responsive to said first timing signal and its associated one of said control signals when said associated one of said counters is below said count threshold to place said associated one of said control signals in a binary 1 condition to produce a signal for coupling to said second logic circuitry to halt the coupling of said first timing signal to said shift register to enable said phase control.

Claim 9

A system according to claim 3, wherein at least one of said third means further includes a timing signal generator to produce at said bit rate a reference signal in the form of a predetermined pattern of binary 1 and binary 0, and the associated one of said digital comparators is coupled to said timing signal generator and said input to compare at said bit rate said reference signal with said successive bits to determine the presence and absence of the associated one of said m sync signals.

Claim 10

A system according to claim 8, wherein said fourth means associated with said one of said third means further includes first logic circuitry coupled betweeN said second means and said timing signal generator to normally couple said first timing signal to said timing signal generator, and second logic circuitry coupled to the associated one of said counters said first logic circuitry and said second means responsive to said first timing signal and the associated one of said control signals when said associated one of said counters is below said count threshold to place said associated one of said control signals in a binary 1 condition to produce a signal for coupling to said first logic circuitry to halt the coupling of said first timing signal to said timing signal generator to enable said phase control.

Claim 11

A system according to claim 3, wherein m is equal to two; one of said third means further includes a first timing signal generator coupled to the input of said comparator to produce a first reference signal and second timing signal to define the time that said sync signals should occur; the other of said third means further includes a second timing signal generator to produce a second reference signal; one of said fourth means includes first logic circuitry coupled between said second means and said second timing signal generator to normally couple said first timing signal to said second timing signal generator; and a first AND gate coupled to the associated one of said counters and said second means responsive to said first timing signal and its associated one of said control signal when its associated one of said counters is below said count threshold to place said associated one of said control signals in a binary 1 condition to produce a first signal for coupling to said first logic circuitry to halt the coupling of said first timing signal to said timing signal generator to enable said phase control; and the other of said fourth means includes second logic circuitry coupled between said second means and said first timing signal generator to normally couple said first timing signal to said first timing signal generator, a second AND gate coupled to the associated one of said counters and said first timing signal generator responsive to said second timing signal and its associated one of said control signals when its associated one of said counters is below said count threshold to place said associated one of said control signals in a binary 1 condition to produce a search enable signal, storage means to store the results of a given number of previous comparisons of its associated one of said comparators, a two input OR gate having one input coupled to the output of its associated one of said comparators, the other input coupled to the output of said storage means and an output coupled to the input of said storage means, and a third AND gate coupled to said second AND gate and the output of said OR gate responsive to a binary 1 output of said OR gate and said search enable signal to produce a signal signal for coupling to said second logic circuitry to halt the coupling of said first timing signal to said timing signal generator to enable said phase control.

Claim 12

A system according to claim 3, wherein m is equal to two; one of said third means includes as its digital comparator a shift register coupled to said input to store said binary data signals at said bit rate, and first logic circuitry coupled to said shift register and the input of the associated one of said counters to examine said successive bits at said bit rate to determine the presence or absence of the associated one of said m sync signals; the other of said third means further includes a timing signal generator to produce a reference signal; one of said fourth means includes second logic circuitry coupled between said second means and said shift register and between said second means and said first logic circuitry to normally couple said first timing signal to said shift register and saiD first logic circuitry, and a first AND gate coupled to the associated one of said counters and said second means responsive to said first timing signal and its associated one of said control signals when its associated one of said counters is below said count threshold to place said associated one of said control signals in a binary 1 condition to produce a first control signal for coupling to said second logic circuitry to halt the coupling of said first timing signal to said shift register and said first logic circuitry to enable said phase control; and the other of said fourth means includes third logic circuitry coupled between said second means and said timing signal generator to normally couple said first timing signal to said timing signal generator, a second AND gate coupled to the associated one of said counters and said second means responsive to said first timing signal and its associated one of said control signals when its associated one of said counters is below said count threshold to place said associated one of said control signals in a binary 1 condition to produce a search enable signal, storage means to store the results of a given number of previous comparisons of its associated one of said comparators, a two input OR gate having one input coupled to the output of its associated one of said comparators, the other input coupled to the output of said storage means and an output coupled to the input of said storage means, and a third AND gate coupled to said second AND gate and the output of said OR gate responsive to a binary 1 output of said OR gate and said search enable signal to produce a second signal for coupling to said third logic circuitry to halt the coupling of said first timing signal to said timing signal generator to enable said phase control.

Claim 13

A system according to claim 1, further including a second source of binary data signals including in each of said predetermined length frame period M time multiplexed groups of time multiplexed channel signals, each of said M groups of channel signals including one of m different sync signals; and wherein said first means is coupled to both said first and second sources and said input to couple said M groups of channel signals of said first source and said M groups of channel signals of said second source time sequentially to said input.

Claim 14

A system according to claim 12, wherein said M groups of channel signals of one of said first and second sources are received at said station, and said M groups of channel signals of the other of said first and second sources are to be transmitted from said station.

Claim 15

A system according to claim 12, wherein said first means includes a second source of pulses having a repetition rate proportional to the length of time to establish said synchronization when any one of said control signals indicate an out-of-synchronization condition, an n stage binary counter coupled to said second source to count said pulses therefrom, where n is an integer greater than one predetermined by the equation 2M 2n, logic decoder coupled to said counter to produce 2M group gate signals determined by the binary condition of said stages of said counter, and a gating arrangement coupled to said decoder, said first and second sources and said input to couple said M groups of channel signals of said first and second source time sequentially to said input.

Claim 16

A system according to claim 14, wherein each of said third means further produces a verify signal having a binary 1 condition at a variable time within a given maximum time to establish synchronization after the associated one of said control signals indicates an out-of-synchronization condition, said verify signal indicating that synchronization has been established, and said second source includes a retriggerable monostable multivibrator producing a pulse having a width equal to said given maximum time, and an (m+1) input OR gate having one input coupled to an output of said monostable multivibrator producing a binary 1 condition responsive to the resetting thereof at the end of said given maximum time, m inputs each coupled to a different one of said third means and responsive to the associated one of said verify signals, and an output to provide said pulses of said second source coupled to said counter at the time one of the inputs to said OR gate first assumes a binary 1 condition, said pulses of said second source coupled to said counter also being coupled to said monostable multivibrator for triggering thereof to restart the production of said pulse having a width equal to said given maximum time and for resetting each of said third means.

Claim 17

A system according to claim 1, wherein said first means includes a second source of pulses having a repetition rate proportional to the length of time to establish said synchronization when any one of said control signals indicate an out-of-synchronization condition, an n stage binary counter coupled to said second source to count said pulses therefrom, where n is an integer greater than one predetermined by the equation M 2n, logic decoder coupled to said counter to produce M group gate signals determined by the binary condition of said stages of said counter, and a gating arrangement coupled to said decoder, said first source and said input to couple said M groups of channel signals of said first source time sequentially to said input.

Claim 18

A system according to claim 16, wherein each of said third means further produces a verify signal having a binary 1 condition at a variable time within a given maximum time to establish synchronization after the associated one of said control signals indicates an out-of-synchronization condition, said verify signal indicating that synchronization has been established, and said second source includes a retriggerable monostable multivibrator producing a pulse having a width equal to said given maximum time, and an (m+1) input OR gate having one input coupled to an output of said monostable multivibrator producing a binary 1 condition responsive to the resetting thereof at the end of said given maximum time, m inputs each coupled to a different one of said third means and responsive to the associated one of said verify signals, and an output to provide said pulses of said second source coupled to said counter at the time one of the inputs to said OR gate first assumes a binary 1 condition, said pulses of said second source coupled to said counter also being coupled to said monostable multivibrator for triggering thereof to restart the production of said pulse having a width equal to said given maximum time and for resetting each of said third means.

Claim 19

A system according to claim 1, further including fifth means coupled to each of said third means and said first means to provide a variable length of search time to establish said synchronization when any one of said control signals indicates an out-of-synchronization condition.

Claim 20

A system according to claim 18, wherein each of said third means further produces a verify signal having a binary 1 condition at a variable time within a given maximum time to establish synchronization after the associated one of said control signals indicates an out-of-synchronization condition, said verify signal indicating that synchronization has been established, and said fifth means includes a retriggerable monostable multivibrator producing a binary 1 condition after said given time, and an OR gate having (m+1) inputs, one input being coupled to said multivibrator and m inputs each coupled to a different one of said third means and responsive to the associated one Of said verify signals, and an output to provide an output binary 1 control signal upon occurrence of the first binary 1 condition appearing on said (m+1) inputs, said output binary 1 control signal being coupled to said multivibrator, each of said third means and said first means for retriggering said multivibrator to restart said given time, to reset each of said third means, and to activate said first means to apply the next of said M groups of channel signals to said input.

Claim 21

A frame synchronization system for a time division multiplex binary data system comprising: a source of binary data time division multiplex signals including in each of repetitive predetermined length frame periods at least one sync signal; first means to produce a timing signal having a frequency equal to the bit rate of said binary data signals; second means coupled to said source and said first means to examine successive bits in each of said frame periods to determine the presence of said sync signal and to produce from said examination a phase control signal in the absence of said sync signal in a given number of successive bits; third means coupled to said second means and said first means responsive to said control signal to control the phase of said timing signal coupled to said second means to establish and maintain synchronization; and fourth means coupled to said second means, said fourth means establishing a given maximum search time which is capable of being interrupted at a variable time within said given time to provide a variable length of search time to establish said synchronization when said control signal indicates an out-of-synchronization condition.

Claim 22

A frame synchronization system for a time division multiplex binary data system comprising: a source of binary data time division multiplex signals including in each of repetitive predetermined length frame periods at least one sync signal; first means to produce a timing signal having a frequency equal to the bit rate of said binary data signals; second means coupled to said source and said first means to examine successive bits in each of said frame periods to determine the presence of said sync signal and to produce from said examination a phase control signal in the absence of said sync signal in a given number of successive bits; third means coupled to said second means and said first means responsive to said control signal to control the phase of said timing signal coupled to said second means to establish and maintain synchronization; and fourth means coupled to said second means, said fourth means establishing a given maximum search time which is capable of being interrupted at a variable time within said given time to provide a variable length of search time to establish said synchronization when said control signal indicates an out-of-synchronization condition.

Claim 23

A system according to claim 20, wherein said second means further produces a verify signal having a binary 1 condition at said variable time within said given time to establish synchronization after said control signal indicates an out-of-synchronization condition, said verify signal indicating that synchronization has been established, and said fourth means includes a retriggerable monostable multivibrator producing a binary 1 condition after said given time, and an OR gate having two inputs, one of said inputs being coupled to said multivibrator and the other input being coupled to said second means responsive to said verify signal, and an output to provide an output binary 1 control signal upon occurrence of the first binary 1 condition appearing on said two inputs, said output binary 1 control signal being coupled to said multivibrator and said second means to retrigger said multivibrator to restart said given time and to reset said second means.