Patent US4597164A successfully refreshed from Google Patents.
US4597164A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Trench isolation process for integrated circuit devices
Assignee: Texas Instruments Inc
•
Filing: 1984-08-31
•
Granted: 1986-07-01
•
Expires: 2004-08-31
Abstract
Abstract Isolation trenches are formed around selected areas on an integrated circuit device, and highly doped areas are formed in the epitaxial silicon surrounding such trenches. The device is then oxidized at a low temperature, and differential oxidation growth of the highly doped areas causes a thick field oxide to grow outside the trenches while only a thin oxide grows over the selected areas.
Inventors
- 👤 Robert H. Havemann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:07
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/014; H10W10/041; H10W10/10; H10W10/13; H10W10/17; H10W10/40; Y; Y10; Y10S; Y10S148/00; Y10S148/082; Y10S438/00; Y10S438/966
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
81 words
A method for isolating a selected area on an integrated circuit device, comprising the steps of: (a) providing a silicon integrated circuit substrate having a selected area thereon; (b) forming a trench around the selected area; (c) forming an insulating barrier in the trench; (d) implanting an N+ dopant in the silicon surrounding the trench; and (e) thermally forming oxide on the surface of the device in the dopant implanted regions at a substantially faster rate than in the selected area.
Claim 2
Independent Claim
81 words
A method for isolating a selected area on an integrated circuit device, comprising the steps of: (a) providing a silicon integrated circuit substrate having a selected area thereon; (b) forming a trench around the selected area; (c) forming an insulating barrier in the trench; (d) implanting an N+ dopant in the silicon surrounding the trench; and (e) thermally forming oxide on the surface of the device in the dopant implanted regions at a substantially faster rate than in the selected area.
Claim 3
Dependent Claim
32 words
The method of claim 1, further comprising the step of: (f) etching the silicon surrounding the trench to a depth approximately one-half the desired thermal oxide depth prior to performing step (d).
Claim 4
Dependent Claim
16 words
The method of claim 1, wherein the selected area comprises an area containing active electronic circuits.
Claim 5
Dependent Claim
10 words
The method of claim 1, wherein the dopant is arsenic.
Claim 6
Dependent Claim
36 words
The method of claim 1, wherein step (d) comprises heating the chip to a temperature which is low enough so that dopants in any active electronic circuits in the selected area undergo no substantial additional diffusion.
Claim 7
Dependent Claim
23 words
The method of claim 1, wherein step (d) comprises heating the chip to a temperature of less than approximately 800° C. in steam.
Claim 8
Dependent Claim
34 words
The method of claim 1, wherein step (c) comprises the steps of: (f) forming a thin layer of thermal oxide in the trench; and (g) filling the remainder of the trench with plasma oxide.
Claim 9
Dependent Claim
18 words
The method of claim 3, wherein the trench is formed after the active circuits have been completely formed.
Claim 10
Dependent Claim
24 words
The method of claim 7, wherein the thin layer of thermal oxide has a depth in the range of approximately 500 to 2000 Angstroms.
Claim 11
Independent Claim
103 words
A method for isolating a selected area on an integrated circuit device, comprising the steps of: (a) providing a silicon integrated circuit substrate having a selected area thereon; (b) forming a masking layer over said selected region; (c) forming a trench around said selected region aligned with an edge of the masking layer; (d) filling the trench with polycrystalline silicon; (e) implanting an N+ dopant in the polycrystalline silicon and in the exposed silicon ouside of the trench; and (f) thermally forming oxide on the surface of the device in the dopant implanted regions at a faster rate than in the selected area.
Claim 12
Independent Claim
103 words
A method for isolating a selected area on an integrated circuit device, comprising the steps of: (a) providing a silicon integrated circuit substrate having a selected area thereon; (b) forming a masking layer over said selected region; (c) forming a trench around said selected region aligned with an edge of the masking layer; (d) filling the trench with polycrystalline silicon; (e) implanting an N+ dopant in the polycrystalline silicon and in the exposed silicon ouside of the trench; and (f) thermally forming oxide on the surface of the device in the dopant implanted regions at a faster rate than in the selected area.
Claim 13
Dependent Claim
40 words
The method of claim 10, further comprising the step of: (g) etching the silicon outside of the trench, and the polycrystalline silicon in the trench, to a depth approximately one-half the desired thermal oxide depth prior to performing step (e).
References Cited (Backward Citations)
US4170492A
Cited
US4356211A
Cited
US4412378A
Cited
US4463493A
Cited
US4502913A
Cited
US4444605A
Cited
US4477310A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-30 | 1989-12-30 | 1990-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-30 | 1993-12-30 | 1994-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-30 | 1997-12-30 | 1998-07-01 | $7700.00 | Window Closed / Lapsed |