Patent US4596014A successfully refreshed from Google Patents.
US4596014A
Expired / Lapsed
US
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I/O rack addressing error detection for process control
Assignee: HF CONTROLS LLP
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Filing: 1984-02-21
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Granted: 1986-06-17
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Expires: 2004-02-21
Abstract
Abstract In an industrial process control system, in which the process is controlled via multiplicity of I/O data points communicating with a computer system controller, errors in the addressing signals selecting the I/O data points are prevented from causing the incorrect setting or reading out incorrect data from wrongly selected data points. A multibit parity signal is generated from the address signals as presented at the output of the computer controller and this parity signal is compared with a second multibit parity signal generated from the address signals as applied to the I/O racks on which the I/O data points are organized. If the parity signals don't compare, the change of the setting of or the read out of valid data from the I/O data point selected by the address signal is prevented. A strobe error detection system is provided in which a strobe pulse applied from the computer system controller to the I/O racks is routed back to the computer system controller where it is compared with the strobe pulse at the output of the computer system controller. The voltage level of the routed back signal is sensed at the leading edge of the strobe pulse at the output of the computer system controller and at the trailing edge of this strobe pulse. If the voltage levels of the routed back signal are not correct, an alarm signal is generated to indicate strobe error.
Inventors
- 👤 James E. Holeman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:11
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/004; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
235 words
A system for detection and prevention of addressing errors comprising a plurality of output data points each settable in accordance with an applied data signal, a computer system, an a multiline connector connected to transmit signals between said computer system and said output data points, said computer system comprising addressing means to generate a multibit address signal and a data signal and to transmit said address signal and said data signal through said connector, data point setting means responsive to an address signal transmitted through said connector from said computer system to select one of said output data points corresponding to the address signal transmitted through said connector and set the selected output data point in accordance with the data signal generated with said address signal and transmitted through said connector, means responsive to the address signal generated by said addressing means before it is applied to said connector to generate a first parity signal, means responsive to the address signal transmitted from said computer system through said connector to generate a second parity signal from the address signal transmitted through said connector, and comparator means to compare said first parity signal with said second parity signal and if said first parity signal does not correspond with said second parity signal to prevent said data point setting means from setting the selected data point in accordance with the data signal generated with said address signal.
Claim 2
Independent Claim
235 words
A system for detection and prevention of addressing errors comprising a plurality of output data points each settable in accordance with an applied data signal, a computer system, an a multiline connector connected to transmit signals between said computer system and said output data points, said computer system comprising addressing means to generate a multibit address signal and a data signal and to transmit said address signal and said data signal through said connector, data point setting means responsive to an address signal transmitted through said connector from said computer system to select one of said output data points corresponding to the address signal transmitted through said connector and set the selected output data point in accordance with the data signal generated with said address signal and transmitted through said connector, means responsive to the address signal generated by said addressing means before it is applied to said connector to generate a first parity signal, means responsive to the address signal transmitted from said computer system through said connector to generate a second parity signal from the address signal transmitted through said connector, and comparator means to compare said first parity signal with said second parity signal and if said first parity signal does not correspond with said second parity signal to prevent said data point setting means from setting the selected data point in accordance with the data signal generated with said address signal.
Claim 3
Dependent Claim
86 words
A system for detection and prevention of addressing errors as recited in claim 1, wherein said data signal comprises at least one binary signal comprising complementary signal voltages, wherein said data point setting means is operable to set an output data point in accordance with said data signal only when the signal voltages of said binary signal are complementary, and wherein said comparator means prevents said data point setting means from setting the selected data point by making said signal voltages comprising said data signal noncomplementary.
Claim 4
Dependent Claim
90 words
A system for detection and prevention of addressing errors as recited in claim 1, wherein said computer system further comprises means to apply a strobe signal over said connector to said data point setting means, wherein said data point setting means sets the selected data point in accordance with said data signal in response to an applied strobe signal, and wherein said comparator means prevents said data point setting means from setting the selected data point by preventing said strobe signal from being applied to said data point setting means.
Claim 5
Dependent Claim
41 words
An industrial process control system comprising a system for detection and prevention of addressing errors as recited in claim 1, and further comprising means to control the parameters of said process in accordance with the settings of said output data points.
Claim 6
Independent Claim
252 words
A system for detection and prevention of addressing errors in an industrial process control system comprising a plurality of input data points each settable to a value in accordance with a process being monitored, a computer system, a multiline connector connected to transmit signals between said computer system and said input data points, said computer system comprising addressing means to generate multibit address signals and to transmit said address signals through said connector, data point readout means responsive to an address signal transmitted through said connector from said computer system to select one of said data points corresponding to the address signal transmitted through said connector, to read out the selected data point, and to transmit a data signal through said connector to said computer system in accordance with the setting of the selected data point, means responsive to each address signal generated by said addressing means before it is applied to said connector to generate a first parity signal and to transmit said partiy signal through said connector, means responsive to the address signal transmitted from said computer system through said connector to generate a second parity signal signal from the address signal transmitted through said connector, comparator means to compare said first parity signal with said second parity signal and, if said first parity signal does not correspond with said second partiy signal to prevent said data point read out means from transmitting to said computer system a data signal recognizable by said computer system as a valid data signal.
Claim 7
Independent Claim
252 words
A system for detection and prevention of addressing errors in an industrial process control system comprising a plurality of input data points each settable to a value in accordance with a process being monitored, a computer system, a multiline connector connected to transmit signals between said computer system and said input data points, said computer system comprising addressing means to generate multibit address signals and to transmit said address signals through said connector, data point readout means responsive to an address signal transmitted through said connector from said computer system to select one of said data points corresponding to the address signal transmitted through said connector, to read out the selected data point, and to transmit a data signal through said connector to said computer system in accordance with the setting of the selected data point, means responsive to each address signal generated by said addressing means before it is applied to said connector to generate a first parity signal and to transmit said partiy signal through said connector, means responsive to the address signal transmitted from said computer system through said connector to generate a second parity signal signal from the address signal transmitted through said connector, comparator means to compare said first parity signal with said second parity signal and, if said first parity signal does not correspond with said second partiy signal to prevent said data point read out means from transmitting to said computer system a data signal recognizable by said computer system as a valid data signal.
Claim 8
Dependent Claim
69 words
A system for detection and prevention of addressing errors in an industrial process control system as recited in claim 5, wherein said data signal comprises at least one binary signal comprising complementary signal voltages, and wherein said comparator means prevents said data point readout means from transmitting a data signal recognizable by said computer system as a valid data signal by making said signal voltages comprising data signal noncomplementary.
Claim 9
Dependent Claim
111 words
A system for detection and prevention of addressing errors in an industrial process control system as recited in claim 5, wherein said computer system further comprises means to apply a strobe signal over said connector to said data point setting means, wherein said data point readout means is responsive to an applied strobe signal to read out the selected data point and to transmit a data signal in accordance with a setting of the selected data point, and wherein said comparator means prevents said data point readout means from transmitting a data signal to said computer system by preventing said strobe signal from being applied to said data point readout means.
Claim 10
Dependent Claim
362 words
A computer control system for controlling industrial process comprising a multiplicity of I/O data points, some of said data points being input data points and some of said data points being output data points, said input data points being settable in accordance with the detected parameters of said process, said output data points being settable in accordance with an applied data signal, means to control parameters of said process in accordance with the setting of said output data point, a computer system, a multiline connector connected to transmit signals between said computer system and said I/O data points, said computer system having addressing means to generate multibit address signals each unique to a different one of said I/O data points, said computer means further comprising means to generate an output data signal representing the value to which an output data point is to be set when said addressing means generates an addressing signal corresponding to an output data point and applying said output data signal to said connector, I/O circuit means responsive to addressing signals transmitted through said connector from said addressing means when said address signal corresponds to an output data point to set such output data point to the value corresponding to the output data signal generated with such addressing signal and applied to said connector and, when said addressing signal is unique to an input data point, to transmit over said connector an input data signal representing the value of such input data point to said computer system, means responsive to the address signal generated by said addressing means before it is applied to said connector to generate a first parity signal, means responsive to the address signal transmitted from said addressing means through said connector to generate a second parity signal, comparator means to compare said first parity signal with said second parity signal and if said first parity signal does not correspond with said second parity signal to prevent said I/O circuit means from setting an output data point in accordance with an output data signal or from applying an input data signal to said computer system recognizable by said computer system as a valid data signal.
Claim 11
Dependent Claim
362 words
A computer control system for controlling industrial process comprising a multiplicity of I/O data points, some of said data points being input data points and some of said data points being output data points, said input data points being settable in accordance with the detected parameters of said process, said output data points being settable in accordance with an applied data signal, means to control parameters of said process in accordance with the setting of said output data point, a computer system, a multiline connector connected to transmit signals between said computer system and said I/O data points, said computer system having addressing means to generate multibit address signals each unique to a different one of said I/O data points, said computer means further comprising means to generate an output data signal representing the value to which an output data point is to be set when said addressing means generates an addressing signal corresponding to an output data point and applying said output data signal to said connector, I/O circuit means responsive to addressing signals transmitted through said connector from said addressing means when said address signal corresponds to an output data point to set such output data point to the value corresponding to the output data signal generated with such addressing signal and applied to said connector and, when said addressing signal is unique to an input data point, to transmit over said connector an input data signal representing the value of such input data point to said computer system, means responsive to the address signal generated by said addressing means before it is applied to said connector to generate a first parity signal, means responsive to the address signal transmitted from said addressing means through said connector to generate a second parity signal, comparator means to compare said first parity signal with said second parity signal and if said first parity signal does not correspond with said second parity signal to prevent said I/O circuit means from setting an output data point in accordance with an output data signal or from applying an input data signal to said computer system recognizable by said computer system as a valid data signal.
Claim 12
Dependent Claim
103 words
A computer control system as recited in claim 8, wherein said data signals are represented by binary signals each comprising complementary signal voltages, wherein said data point setting means is operable to set an output data point in accordance with said data signal only when the signal voltages of said binary signal are complementary, and wherein said comparator means prevents said I/O circuit means from setting a selected output data point and prevents said I/O circuit means from applying an input data signal recognizable by said computer system as a valid data signal by making said signal voltages comprising said data signals noncomplementary.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-16 | 1989-12-16 | 1990-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-16 | 1993-12-16 | 1994-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-16 | 1997-12-16 | 1998-06-17 | $7700.00 | Window Closed / Lapsed |