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US4594728A
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Synchronization device for digital frame transmission
Assignee: Lignes Telegraphiques et Telephoniques LTT SA
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Filing: 1984-06-26
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Granted: 1986-06-10
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Expires: 2004-06-26
Abstract
Abstract A synchronization device for digital data frame transmission system comprising an n bit series register transferring its contents at the line frequency to a parallel register also of n bits. The m first bits of the series register are also directed to a logic circuit which tests their conformity with the beginning of the synchronization word. When there is conformity, the logic circuit controls a divider dividing by n which controls, in its turn, at the line frequency divided by n, the transfer of the contents of the parallel register to a PROM memory. The purpose of the PROM is to recognize the entire synchronization word. When there is no recognition, the operation of the divide by n divider is inhibited and the procedure begins again.
Inventors
- 👤 Maurice Niquel
- 👤 Claude Gourdon
- 👤 Jean Rouxel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:56
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
198 words
A synchronization device for digital transmission of data with frames, the data transmitted being received in series in binary form and comprising a synchronization signal having a total number p of bits, the device further receiving a clock signal (H), representing the line frequency of the transmission, said device comprising a series register with n positions, receiving said binary data; a parallel register with n positions, receiving in parallel the contents of said series register when triggered by said clock signal (H); a logic circuit connected to an output of said series register and ensuring detection of a first m bits of said total number p of bits of said synchronization signal and delivering a recognition signal when said m bits are detected; a divider dividing said clock signal by n, said divider being controlled by said recognition signal (C D ); a memory, receiving in parallel the contents of said parallel register when said contents are released therefrom under control (C T ) of said divider, said memory ensuring recognition of said synchronization signal by words of n bits and supplying a signal (I) inhibiting the operation of said divider when said synchronization signal is not recognized.
Claim 2
Dependent Claim
198 words
A synchronization device for digital transmission of data with frames, the data transmitted being received in series in binary form and comprising a synchronization signal having a total number p of bits, the device further receiving a clock signal (H), representing the line frequency of the transmission, said device comprising a series register with n positions, receiving said binary data; a parallel register with n positions, receiving in parallel the contents of said series register when triggered by said clock signal (H); a logic circuit connected to an output of said series register and ensuring detection of a first m bits of said total number p of bits of said synchronization signal and delivering a recognition signal when said m bits are detected; a divider dividing said clock signal by n, said divider being controlled by said recognition signal (C D ); a memory, receiving in parallel the contents of said parallel register when said contents are released therefrom under control (C T ) of said divider, said memory ensuring recognition of said synchronization signal by words of n bits and supplying a signal (I) inhibiting the operation of said divider when said synchronization signal is not recognized.
Claim 3
Dependent Claim
40 words
The device as claimed in claim 1, wherein the binary data received are cut up into words of n bits, said logic circuit detecting m bits with m<n, and said synchronization signal being expressed over a word of n bits.
Claim 4
Dependent Claim
40 words
The device as claimed in claim 1, wherein said binary data received are cut up into words of n bits, said logic circuit detecting m=n bits and said synchronization signal being expressed over a number of bits greater than n.
Claim 5
Dependent Claim
15 words
The device as claimed in claim 1, wherein said memory is of the PROM type.
Claim 6
Dependent Claim
20 words
The device as claimed in claim 1, further comprising means for preventing reception of said inhibition signal by said divider.
Claim 7
Dependent Claim
13 words
The device as claimed in claim 1, wherein said divider comprises a counter.
Claim 8
Dependent Claim
39 words
The device as claimed in claim 1, wherein said logic circuit comprises a second series register containing the first m bits contained in said first series register, and a logic circuit of the combinative type delivering said recognition signal.
Claim 9
Dependent Claim
17 words
The device as claimed in claim 1, whose output is formed by the input of said memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-09 | 1989-12-09 | 1990-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-09 | 1993-12-09 | 1994-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-09 | 1997-12-09 | 1998-06-10 | $7700.00 | Window Closed / Lapsed |