US3603735A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronizing arrangement for a pulse-communication receiver
Assignee: The General Electric Company PLC
•
Filing: 1969-07-07
•
Granted: 1971-09-07
•
Expires: 1989-07-07
Abstract
Abstract A pulse-code-modulation synchronizing arrangement for a system using a synchronizing pulse pattern having a first simple portion which occurs commonly at random in the transmitted signal and a second more extensive portion which is highly improbable at random. The receiver, in seeking synchronism, resets its phase at each genuine and false occurrence of the simple portion. Synchronism is confirmed if no further reset occurs during the extent of the second portion (which does not contain the simple portion). The above resetting is on a channel basis: digit synchronism is achieved by slipping a digit periodically with sufficient intervening time to obtain overall synchronism by channel resetting if the digit phase is in fact correct. Loss or absence of synchronism is rapidly determined by the closely repeated presence of the common first portion.
Inventors
- 👤 Donald Jack Cleobury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:16
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
116 words
A synchronizing arrangement for a time-division-multiplex pulse-code-modulation receiver, comprising first circuit means responsive to a first portion of a synchronizing pulse pattern to reset the phase of operation of the receiver to a predetermined phase reference, said first portion being of common occurrence at random in the received signal so that in the absence of synchronism repeated phase resetting occurs, and second circuit means responsive to a second portion of the synchronizing pulse pattern when received in predetermined time relation with said first portion in a predetermined number of successive cycles of said synchronizing pulse pattern to inhibit said first circuit means, said second portion of the synchronizing pulse pattern being of relatively rare random occurrence.
Claim 2
Dependent Claim
116 words
A synchronizing arrangement for a time-division-multiplex pulse-code-modulation receiver, comprising first circuit means responsive to a first portion of a synchronizing pulse pattern to reset the phase of operation of the receiver to a predetermined phase reference, said first portion being of common occurrence at random in the received signal so that in the absence of synchronism repeated phase resetting occurs, and second circuit means responsive to a second portion of the synchronizing pulse pattern when received in predetermined time relation with said first portion in a predetermined number of successive cycles of said synchronizing pulse pattern to inhibit said first circuit means, said second portion of the synchronizing pulse pattern being of relatively rare random occurrence.
Claim 3
Dependent Claim
28 words
A synchronizing arrangement according to claim 1 wherein said first and second circuit means are responsive to signals received in predetermined digit time-slots occurring at the channel spacing.
Claim 4
Dependent Claim
93 words
A synchronizing arrangement according to claim 2, wherein said first circuit means effects a phase resetting equivalent to an integral number of channel time slots, the arrangement further comprising digit reset means for periodically changing the phase of operation of the receiver by a fraction of a channel time slot so as to scan the digit time slots for the synchronizing pulse pattern, said digit reset means being inhibited by said second circuit means in response to reception of a said second portion of the synchronizing pulse pattern in said predetermined time relation.
Claim 5
Dependent Claim
92 words
A synchronizing arrangement according to claim 3, wherein said second portion of the synchronizing pulse pattern is of substantially greater extent than said first portion and has no part identical with said first portion, and wherein said second circuit means produces an inhibiting signal at the attainment of a point in the multiplex cycle which point follows said phase reference after an interval corresponding to the extent of said second portion of the synchronizing pulse pattern, said inhibiting signal constituting an indication of synchronism and being applied to inhibit said digit-reset means.
Claim 6
Dependent Claim
68 words
A synchronizing arrangement according to claim 4, including first bistable storage means which adopts a synchronism state in response to the coincident occurrence of a said first portion of the synchronizing pulse pattern and said phase reference, said first bistable storage means adopting an error state in response to the occurrence of a said first portion of the synchronizing pulse pattern in the absence of said phase reference.
Claim 7
Dependent Claim
60 words
A synchronizing arrangement according to claim 5, wherein said first bistable storage means is responsive to a further pulse pattern which occurs commonly at random in the received signal and which is not contained in said second portion of the synchronizing pulse pattern, said first bistable storage means being responsive to said further pulse pattern to adopt said error state.
Claim 8
Dependent Claim
113 words
A synchronizing arrangement according to claim 5, and comprising a shift register for which the states of said first bistable storage means supply steering signals, said indications of synchronism constituting stepping signals for the shift register, and further bistable storage means responsive to said first storage means and to said shift register, the further storage means adopting an error state in response to the presence of coincident error states of the first storage means and of the stages of the shift register, and the further storage means adopting a synchronism state in response to the presence of coincident synchronism states of the first storage meAns and of the stages of the shift register.
Claim 9
Dependent Claim
25 words
A synchronizing arrangement according to claim 5, wherein said digit reset means is inhibited in response to the synchronism state of said first storage means.
Claim 10
Dependent Claim
34 words
A synchronism arrangement according to claim 1, wherein said first portion of the synchronizing pulse pattern comprises the digits 11'' and said second portion comprises a number of the digit pairs ''01'' in sequence.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-06 | 1975-03-08 | 1975-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-06 | 1979-03-08 | 1979-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-06 | 1983-03-08 | 1983-09-07 | $7700.00 | Window Closed / Lapsed |