Patent US4593459A successfully refreshed from Google Patents.
US4593459A
Expired / Lapsed
US
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Monolithic integrated circuit structure and method of fabrication
Assignee: Verizon Laboratories Inc
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Filing: 1984-12-28
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Granted: 1986-06-10
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Expires: 2004-12-28
Abstract
Abstract Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.
Inventors
- 👤 Paul E. Poppert
- 👤 Marvin J. Tabasky
- 👤 Eugene O. Degenkolb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:11
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0188; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/014; H10W10/0143; H10W10/0145; H10W10/041; H10W10/10; H10W10/13; H10W10/17; H10W10/40; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; Y; Y10; Y10S; Y10S148/00; Y10S148/07; Y10S148/085; Y10S148/086
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
232 words
The method of producing a substrate for the fabrication of semiconductor integrated circuit devices therein comprising providing a body of semiconductor material having an underlying layer of one conductivity type and having a first section of one conductivity type and a second section of the opposite conductivity type at a surface of the body, said first and second sections being contiguous at a junction in said body of semiconductor material and said first and second sections each being contiguous with said underlying layer at an interface parallel with said surface; forming grooves in said first and second sections extending from said surface to below said interface to provide a first isolated sector of said first section encircled by grooves and a second isolated sector of said second section encircled by grooves; forming a coating of adherent nonconductive protective material on the exposed semiconductor material of said grooves; filling said grooves with a semiconductor fill material; forming a coating of adherent nonconductive protective material on the surface of the semiconductor fill material adjacent to said surface of the body to enclose said semiconductor fill material with nonconductive protective material; removing semiconductor material from a portion of said first and second sections at said junction to form a trench extending into said body from said surface between said grooves of said first and second sections; and filling said trench with adherent nonconductive protective material.
Claim 2
Independent Claim
232 words
The method of producing a substrate for the fabrication of semiconductor integrated circuit devices therein comprising providing a body of semiconductor material having an underlying layer of one conductivity type and having a first section of one conductivity type and a second section of the opposite conductivity type at a surface of the body, said first and second sections being contiguous at a junction in said body of semiconductor material and said first and second sections each being contiguous with said underlying layer at an interface parallel with said surface; forming grooves in said first and second sections extending from said surface to below said interface to provide a first isolated sector of said first section encircled by grooves and a second isolated sector of said second section encircled by grooves; forming a coating of adherent nonconductive protective material on the exposed semiconductor material of said grooves; filling said grooves with a semiconductor fill material; forming a coating of adherent nonconductive protective material on the surface of the semiconductor fill material adjacent to said surface of the body to enclose said semiconductor fill material with nonconductive protective material; removing semiconductor material from a portion of said first and second sections at said junction to form a trench extending into said body from said surface between said grooves of said first and second sections; and filling said trench with adherent nonconductive protective material.
Claim 3
Dependent Claim
27 words
The method in accordance with claim 1 wherein said body of semiconductor material is of single crystal silicon; and said semiconductor fill material is of polycrystalline silicon.
Claim 4
Dependent Claim
16 words
The method in accordance with claim 2 wherein said adherent nonconductive protective material is silicon dioxide.
Claim 5
Dependent Claim
41 words
The method in accordance with claim 3 wherein forming a coating of an adherent nonconductive protective material on the exposed semiconductor material of said grooves includes exposing the body of silicon to oxygen at an elevated temperature to grow silicon dioxide.
Claim 6
Dependent Claim
168 words
The method in accordance with claim 4 wherein providing a body of semiconductor material includes providing a wafer of semiconductor material of the one conductivity type having a flat planar surface; growing an epitaxial layer of semiconductor material of the one conductivity type of relatively high resistivity on said surface of the wafer, said epitaxial layer having a flat planar surface parallel to the interface of the epitaxial layer and the wafer, said wafer and said epitaxial layer forming the body of semiconductor material; and introducing conductivity type imparting material of the one conductivity type into a first section of said epitaxial layer from the surface to the interface of the epitaxial layer and the wafer to form said first section of the one conductivity type and introducing conductivity type imparting material of the opposite conductivity type into a second section of said epitaxial layer from the surface to the interface of the epitaxial layer and the wafer to form a second section of the opposite conductivity type.
Claim 7
Independent Claim
438 words
The method of fabricating monolithic integrated circuit structure incorporating complementary field effect transistors comprising providing a body of semiconductor material having an underlying layer of one conductivity type and having a first section of one conductivity type and a second section of the opposite conductivity type at a surface of the body, said first and second sections being contiguous at a junction in said body of semiconductor material and said first and second sections each being contiguous with said underlying layer at an interface parallel with said surface; forming grooves in said first and second sections extending from said surface to below said interface to provide a first isolated sector of said first section encircled by grooves and a second isolated sector of said second section encircled by grooves; forming a coating of adherent nonconductive protective material on the exposed semiconductor material of said grooves; filling said grooves with a semiconductor fill material; forming a coating of adherent nonconductive protective material on the surface of the semiconductor fill material adjacent to said surface of the body to enclose said semiconductor fill material with nonconductive protective materials; removing semiconductor material from a portion of said first and second sections at said junction to form a trench extending into said body from said surface between said grooves of said first and second sections; filling said trench with adherent nonconductive protective material; placing an adherent gate layer of insulating material on the surface of said first and second sectors; placing a first gate member of semiconductor material of low resistivity over a portion of the gate layer of insulating material overlying a channel region of said first sector with said channel region lying between two source/drain regions of said first sector, and a second gate member of semiconductor material of low resistivity over a portion of the gate layer of insulating material overlying a channel region of said second sector with said channel region lying between two source/drain regions of said second sector; introducing conductivity type imparting material of the opposite conductivity type into said two source/drain regions of said first sector, and introducing conductivity type imparting material of the one conductivity type into said two source/drain regions of said second sector; removing insulating material to expose areas of said two source/drain regions of said first sector and areas of said two source/drain regions of said second sector at said surface; and forming adherent conductive connections in ohmic contact with said areas, one of said connections connecting a source/drain region of said first sector and a source/drain region of said second sector and overlying said nonconductive protective material filling said trench.
Claim 8
Independent Claim
438 words
The method of fabricating monolithic integrated circuit structure incorporating complementary field effect transistors comprising providing a body of semiconductor material having an underlying layer of one conductivity type and having a first section of one conductivity type and a second section of the opposite conductivity type at a surface of the body, said first and second sections being contiguous at a junction in said body of semiconductor material and said first and second sections each being contiguous with said underlying layer at an interface parallel with said surface; forming grooves in said first and second sections extending from said surface to below said interface to provide a first isolated sector of said first section encircled by grooves and a second isolated sector of said second section encircled by grooves; forming a coating of adherent nonconductive protective material on the exposed semiconductor material of said grooves; filling said grooves with a semiconductor fill material; forming a coating of adherent nonconductive protective material on the surface of the semiconductor fill material adjacent to said surface of the body to enclose said semiconductor fill material with nonconductive protective materials; removing semiconductor material from a portion of said first and second sections at said junction to form a trench extending into said body from said surface between said grooves of said first and second sections; filling said trench with adherent nonconductive protective material; placing an adherent gate layer of insulating material on the surface of said first and second sectors; placing a first gate member of semiconductor material of low resistivity over a portion of the gate layer of insulating material overlying a channel region of said first sector with said channel region lying between two source/drain regions of said first sector, and a second gate member of semiconductor material of low resistivity over a portion of the gate layer of insulating material overlying a channel region of said second sector with said channel region lying between two source/drain regions of said second sector; introducing conductivity type imparting material of the opposite conductivity type into said two source/drain regions of said first sector, and introducing conductivity type imparting material of the one conductivity type into said two source/drain regions of said second sector; removing insulating material to expose areas of said two source/drain regions of said first sector and areas of said two source/drain regions of said second sector at said surface; and forming adherent conductive connections in ohmic contact with said areas, one of said connections connecting a source/drain region of said first sector and a source/drain region of said second sector and overlying said nonconductive protective material filling said trench.
Claim 9
Dependent Claim
27 words
The method in accordance with claim 6 wherein said body of semiconductor material is of single crystal silicon; and said semiconductor fill material is of polycrystalline silicon.
Claim 10
Dependent Claim
16 words
The method in accordance with claim 7 wherein said adherent nonconductive protective material is silicon dioxide.
Claim 11
Dependent Claim
21 words
The method in accordance with claim 8 wherein said first and second gate members of semiconductor material are of polycrystalline silicon.
Claim 12
Dependent Claim
18 words
The method in accordance with claim 9 wherein said adherent gate layer of insulating material is silicon dioxide.
Claim 13
Dependent Claim
41 words
The method in accordance with claim 10 wherein forming a coating of an adherent nonconductive protective material on the exposed semiconductor material of said grooves includes exposing the body of silicon to oxygen at an elevated temperature to grow silicon dioxide.
Claim 14
Dependent Claim
168 words
The method in accordance with claim 11 wherein producing a body of semiconductor material includes providing a wafer of semiconductor material of the one conductivity type having a flat planar surface; growing an epitaxial layer of semiconductor material of the one conductivity type of relatively high resistivity on said surface of the wafer, said epitaxial layer having a flat planar surface parallel to the interface of the epitaxial layer and the wafer, said wafer and said epitaxial layer forming the body of semiconductor material; and introducing conductivity type imparting material of the one conductivity type into a first section of said epitaxial layer from the surface to the interface of the epitaxial layer and the wafer to form said first section of the one conductivity type and introducing conductivity type imparting material of the opposite conductivity type into a second section of said epitaxial layer from the surface to the interface of the epitaxial layer and the wafer to form a second section of the opposite conductivity type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-09 | 1989-12-09 | 1990-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-09 | 1993-12-09 | 1994-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-09 | 1997-12-09 | 1998-06-10 | $7700.00 | Window Closed / Lapsed |