Full adder using complementary MOSFETs

Claim 2

A full adder comprising: a first logic circuit having first signal inverting means which receives a first input signal and produces a first output signal, and first signal selecting means which receives said first input and said first output signal and produces a second output signal which is equal to one of said first input signal or said first output signal depending on the state of a second input signal; a second logic circuit having second signal inverting means which receives said second output signal and produces a third output signal, and second signal selecting means which receives said second output signal and said third output signals and produces a fourth output signal which is equal to one of said second or third outputs signal depending on the state of a third input signal; and a third logic circuit which receives said first output signal and said fourth output signal and produces a fifth output signal which is equal to one of said last-mentioned signals depending on the state of said third output signal.

Claim 3

A full adder according to claim 1, wherein said fourth output signal is the sum of said first, second and third input signals.

Claim 4

A full adder according to claim 1, wherein said third logic circuit comprises third signal inverting means and third signal selecting means.

Claim 5

A full adder according to claim 3, wherein said third signal selecting means receives said fourth output signal and said first output signal and produces said fifth output signal in response to the state of said third output signal, and said third signal inverting means receives said fifth output signal.

Claim 6

A full adder according to claim 4, wherein said third signal selecting means comprises two MOSFETs of different conductivity types whose output terminals are connected to each other, said first output signal and said fourth output signal are supplied to the free ends of said two MOSFETs, said third output signal is supplied to the gates of said two MOSFETs, and said fifth output signal is obtained at the connection point between said output terminals of said two MOSFETs.

Claim 7

A full adder according to claim 3, wherein each of said first and second signal selecting means comprises two MOSFETs of different conductivity types whose output terminals are connected to each other, in said first signal selecting means, said first output signal and said first input signal are supplied to the free ends of said two MOSFETs, said second input signal is supplied to the gates of said two MOSFETs, and said second output signal is obtained at the connection point between said output terminals of said two MOSFETs, and in said second signal selecting means, said second output signal and said third output signal are supplied to the free ends of said two MOSFETs, said third input signal is supplied to the gates of said two MOSFETs, and said fourth output signal is obtained at the connecting point between said output terminals of said two MOSFETs.

Claim 8

An operation circuit including a plurality of full adders each of which comprises: a first logic circuit having first signal inverting means which receives a first input signal and produces a first output signal, and first signal selecting means which receives said first input signal and said first output signal and produces a second output signal which is equal to one of said first input signal or said first output signal depending on the state of a second input signal; a second logic circuit having second signal inverting means which receives said second output signal and produces a third output signal, and second signal selecting means which receives said second output signal and said third output signal and produces a fourth output signal which is equal to one of said second or third output signals depending on the state of a third input signal; and a third logic circuit which receives said first output signal and said fourth output signal and produces a fifth output signal which is equal to one of said last-mentioned signals depending on the state of said third output signal.

Claim 9

An operation circuit including a plurality of full adders each of which comprises: a first logic circuit having first signal inverting means which receives a first input signal and produces a first output signal, and first signal selecting means which receives said first input signal and said first output signal and produces a second output signal which is equal to one of said first input signal or said first output signal depending on the state of a second input signal; a second logic circuit having second signal inverting means which receives said second output signal and produces a third output signal, and second signal selecting means which receives said second output signal and said third output signal and produces a fourth output signal which is equal to one of said second or third output signals depending on the state of a third input signal; and a third logic circuit which receives said first output signal and said fourth output signal and produces a fifth output signal which is equal to one of said last-mentioned signals depending on the state of said third output signal.

Claim 10

A binary adder circuit receiving first, second and third binary input signals and producing binary sum and carry output signals in response thereto, comprising: a first stage including complementary MOSFET inverter means and complementary MOSFET selector means, said inverter means receiving said first input signal and producing an inverted first input signal and said selector means receiving said first input signal, said inverted first input signal and said second input signal and generating a first intermediate output signal which is equal to either said first input signal or said inverted first input signal depending on the binary state of said second input signal; a second stage including complementary MOSFET inverter means and complementary MOSFET selector means, said inverter means receiving said first intermediate output signal and producing an inverted first intermediate output signal and said selector means receiving said first intermediate output signal, said inverted first intermediate output signal and said third input signal and generating said sum output signal which is equal to either said first intermediate output signal or said inverted first intermediate output signal depending on the binary state of said third input signal; and a third stage including complementary MOSFET inverter means and complementary MOSFET selector means, said selector means receiving said sum output signal, said inverted first input signal, and said inverted first intermediate output signal and generating a second intermediate output signal which is equal to either said sum output signal or said inverted first input signal depending on the binary state of said inverted first intermediate output signal, and said inverter means receiving said second intermediate output signal and inverting it to produce said carry output signal.

Claim 11

A binary adder circuit receiving first, second and third binary input signals and producing binary sum and carry output signals in response thereto, comprising: a first stage including complementary MOSFET inverter means and complementary MOSFET selector means, said inverter means receiving said first input signal and producing an inverted first input signal and said selector means receiving said first input signal, said inverted first input signal and said second input signal and generating a first intermediate output signal which is equal to either said first input signal or said inverted first input signal depending on the binary state of said second input signal; a second stage including complementary MOSFET inverter means and complementary MOSFET selector means, said inverter means receiving said first intermediate output signal and producing an inverted first intermediate output signal and said selector means receiving said first intermediate output signal, said inverted first intermediate output signal and said third input signal and generating said sum output signal which is equal to either said first intermediate output signal or said inverted first intermediate output signal depending on the binary state of said third input signal; and a third stage including complementary MOSFET inverter means and complementary MOSFET selector means, said selector means receiving said sum output signal, said inverted first input signal, and said inverted first intermediate output signal and generating a second intermediate output signal which is equal to either said sum output signal or said inverted first input signal depending on the binary state of said inverted first intermediate output signal, and said inverter means receiving said second intermediate output signal and inverting it to produce said carry output signal.

Claim 12

A full adder comprising: a first logic circuit having first signal inverting means which receives a first input signal and produces a first output signal, and first signal selecting means which receives said first input and said first output signal and produces a second output signal which is equal to one of said first input signal or said first output signal depending on the state of a second input signal; a second logic circuit having second signal inverting means which receives said second output signal and produces a third output signal, and second signal selecting means which receives said second output signal and said third output signal and produces a fourth output signal which is equal to one of said second or third output signals depending on the state of a third input signal; and a third logic circuit which receives said first input signal and said fourth output signal and produces a fifth output signal which is equal to said first input signal or the complement of said fourth output signal depending on the state of said third output signal.

Claim 13

A full adder comprising: a first logic circuit having first signal inverting means which receives a first input signal and produces a first output signal, and first signal selecting means which receives said first input and said first output signal and produces a second output signal which is equal to one of said first input signal or said first output signal depending on the state of a second input signal; a second logic circuit having second signal inverting means which receives said second output signal and produces a third output signal, and second signal selecting means which receives said second output signal and said third output signal and produces a fourth output signal which is equal to one of said second or third output signals depending on the state of a third input signal; and a third logic circuit which receives said first input signal and said fourth output signal and produces a fifth output signal which is equal to said first input signal or the complement of said fourth output signal depending on the state of said third output signal.

Claim 14

A full adder according to claim 9, wherein said fourth output signal is the sum of said first, second and third input signals.

Claim 15

A full adder according to claim 9, wherein said third logic circuit comprises third signal inverting means and third signal selecting means.

Claim 16

A full adder according to claim 11, wherein said third signal inverting means receives said fourth output signal and produces said complement of said fourth output signal and said third signal selecting means receives said complement of said fourth output signal and said first input signal and produces said fifth output signal in response to the state of said third output signal.

Claim 17

A full adder according to claim 11, wherein each of said first and second signal selecting means comprises two MOSFETs of different conductivity types whose output terminals are connected to each other, in said first signal selecting means, said first output signal and said first input signal are supplied to the free ends of said two MOSFETs, said second input signal is supplied to the gates of said two MOSFETs, and said second output signal is obtained at the connection point between said output terminals of said two MOSFETs, and in said second signal selecting means, said second output signal and said third output signal are supplied to the free ends of said two MOSFETs, said third input signal is supplied to the gates of said two MOSFETs, and said fourth output signal is obtained at the connecting point between said output terminals of said two MOSFETs.

Claim 18

A full adder according to claim 13, wherein said third signal selecting means comprises two MOSFETs of different conductivity types whose output terminals are connected to each other, said first input signal and said complement of said fourth output signal are supplied to the free ends of said two MOSFETs, said third output signal is supplied to the gates of said two MOSFETs, and said fifth output signal is obtained at the connection point between said output terminals of said two MOSFETs.