US3843876A
Expired / Lapsed
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Electronic digital adder having a high speed carry propagation line
Assignee: Motorola Solutions Inc
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Filing: 1973-09-20
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Granted: 1974-10-22
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Expires: 1993-09-20
Abstract
Abstract A parallel, binary adder has extremely high speed carry propagation capabilities. The sum and the carry generated in each stage are developed simultaneously and share much of the same circuitry. In a preferred embodiment utilizing metal oxide semiconductor field-effect transistors, a carry propagation line is charged prior to the addition and carry generation and then is simply discharged or not discharged, depending on the outcome of the computation. In four of the eight possible combinations of inputs to generate a carry-out signal, a carry-in gate is activated, providing a path with no other logic gates and permitting a high speed ripple of the carry signal.
Inventors
- 👤 B Fette
- 👤 L Hazlett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:50
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/503; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3872
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
291 words
A digital adder including N-parallel full adder stages, each stage adaptive to receive its associated addend input signal A, its associated augend input signal B, and a carry-in signal C, for providing a carry-out signal K and a sum signal S, a plurality of the adder stages each comprising: a. first MOS inverter mode logic means responsive to its associated addend input signal A and its associated augend input signal B for providing a first carry-out control signal at a first output means when its associated A and B input signals are both at a first predetermined level, and a second carry-out control signal at a second output means when its associated A and B input signals are at opposite levels; b. a carry propagation line means serially interconnecting a plurality of the stages; c. an MOS carry-in device gate means connected to said second output means and to said carry propagation line means for receiving a carry-in signal C from a lower order stage and being selectively responsive to said second carry-out control signal for generating a carry-out signal K for a higher order stage; d. an MOS carry-out device gate means connected to said first output means and to said carry propagation line means for selectively providing a carry-out signal K for a higher order stage in response to the first carry-out control signal; e. a second MOS inverter mode logic means connected to said second output means and to said carry propagation line means from a lower order stage for selectively generating an output signal S in response to its associated A and B input signals and a carry-in signal C from a lower order stage; and f. means for setting said propagation lines to a predetermined level.
Claim 2
Dependent Claim
291 words
A digital adder including N-parallel full adder stages, each stage adaptive to receive its associated addend input signal A, its associated augend input signal B, and a carry-in signal C, for providing a carry-out signal K and a sum signal S, a plurality of the adder stages each comprising: a. first MOS inverter mode logic means responsive to its associated addend input signal A and its associated augend input signal B for providing a first carry-out control signal at a first output means when its associated A and B input signals are both at a first predetermined level, and a second carry-out control signal at a second output means when its associated A and B input signals are at opposite levels; b. a carry propagation line means serially interconnecting a plurality of the stages; c. an MOS carry-in device gate means connected to said second output means and to said carry propagation line means for receiving a carry-in signal C from a lower order stage and being selectively responsive to said second carry-out control signal for generating a carry-out signal K for a higher order stage; d. an MOS carry-out device gate means connected to said first output means and to said carry propagation line means for selectively providing a carry-out signal K for a higher order stage in response to the first carry-out control signal; e. a second MOS inverter mode logic means connected to said second output means and to said carry propagation line means from a lower order stage for selectively generating an output signal S in response to its associated A and B input signals and a carry-in signal C from a lower order stage; and f. means for setting said propagation lines to a predetermined level.
Claim 3
Dependent Claim
79 words
A digital adder including N-parallel full adder stages, each stage adaptive to receive its associated addend input signal A, its associated augend input signal B, and a carry-in signal C, for providing a carry-out signal K and a sum signal S, as in claim 1 wherein: a. said first MOS inverter mode logic means includes means for providing an AND logic function at said first output means, and means for providing an Exclusive-NOR function at said second output means.
Claim 4
Dependent Claim
62 words
A digital adder including N-parallel full adder stages, each stage adaptive to receive its associated addend input signal A, its associated augend input signal B, and a carry-in signal C, for providing a carry-out signal K and a sum signal S, as in claim 2 wherein: a. said MOS carry-in and carry-out device gate means each comprise a single channel MOS device.
Claim 5
Dependent Claim
84 words
A digital adder including N-parallel full adder stages, each stage adaptive to receive its associated addend input signal A, its associated augend input signal B, and a carry-in signal C, for providing a carry-out signal K and a sum signal S, as in claim 3 wherein: a. said means for setting said carry propagation lines to a predetermined level comprises a third MOS device gate means responsive to clock pulsEs for selectively and periodically setting said carry propagation line means to a predetermined level.
Claim 6
Dependent Claim
61 words
A digital adder including N-parallel full adder stages, each stage adaptive to receive its associated addend input signal A, its associated augend input signal B, and a carry-in signal C, for providing a carry-out signal K and a sum signal S, as in claim 3 wherein: a. said second MOS inverter mode logic means comprises means for providing an Exclusive-NOR function.
Claim 7
Dependent Claim
62 words
A digital adder including N-parallel full adder stages, each stage adaptive to receive its associated addend input signal A, its associated augend input signal B, and a carry-in signal C, for providing a carry-out signal K and a sum signal S, as in claim 5 wherein: a. said first and second MOS inverter mode logic means each comprise single channel MOS devices.
Claim 8
Dependent Claim
59 words
A digital adder including N-parallel full adder stages, each stage adaptive to receive its associated addend input signal A, its associated augend input signal B, and a carry-in signal C, for providing a carry-out signal K and a sum signal S, as in claim 2 wherein: a. said MOS carry-in and carry-out device gate means each comprise CMOS devices.
Claim 9
Dependent Claim
59 words
A digital adder including N-parallel full adder stages, each stage adaptive to receive its associated addend input signal A, its associated augend input signal B, and a carry-in signal C, for providing a carry-out signal K and a sum signal S, as in claim 7 wherein: a. said first and second inverter mode logic means each comprises CMOS devices.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-21 | 1978-04-22 | 1978-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-21 | 1982-04-22 | 1982-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-21 | 1986-04-22 | 1986-10-22 | $7700.00 | Window Closed / Lapsed |