Microcomputer with power-save output instructions

Claim 2

A microcomputer having an operation state and a power-save state, said microcomputer being responsive to a power-save instruction to reduce its own power consumption by entering said power-save state, and being responsive to an externally-supplied interruption signal to return to an operation state from said power-save state, said microcomputer comprising: a memory for storing instructions, including said power-save instruction, for execution by said microcomputer; an instruction decoded coupled to said memory for generating a power-save signal corresponding to said power-save instruction; a flip-flop circuit for providing a power-save output signal, said flip-flop having a set terminal coupled to the power-save signal of the instruction decoder and a reset terminal coupled to said externally-supplied interruption signal; a clock generator for supplying clock signals to said microcomputer, said clock generator including means for receiving said power-save signal from the instruction decoder and turning off said clock signals in response to said power-save instruction; and input means connected to said set terminal of said flip-flop for an externally supplied power-save signal.

Claim 3

A microcomputer having an operation state and a power-save state, said microcomputer being connected to at least one peripheral circuit and responsive to a power-save instruction to reduce its own power consumption by entering said power-save state, and being connected to an externally-supplied interruption signal to return to said operation state from said power-save state, said micrcomputer comprising: memory means for storing instructions to be executed by said microcomputer, including said power-save instruction; means for decoding instructions from said memory means when said microcomputer is in said operation state and for outputting a power-save signal in response to said power-save instruction; signal outputting means connected to said decoding means and coupled to said externally-supplied interruption signal for outputting from said microcomputer to said at least one peripheral circuit a power-save mode signal in response to said power-save signal, said power-save mode signal indicating that said microcomputer is in said power-save state and said power-save mode signal continuing until said microcomputer receives said externally-supplied interruption signal; clock generating means for supplying timing signals to said microcomputer; clock control means connected to said clock generating means and to said decoder means for stopping all said timing signals to said microcomputer in response to said power-save signal and thereby placing said microcomputer in said power-save state; and input means connected to said signal outputting means for accepting an externally supplied power-save signal.

Claim 4

A microcomputer having an operation state and a power-save state, said microcomputer being connected to at least one peripheral circuit and responsive to a power-save instruction to reduce its own power consumption by entering said power-save state, and being connected to an externally-supplied interruption signal to return to said operation state from said power-save state, said micrcomputer comprising: memory means for storing instructions to be executed by said microcomputer, including said power-save instruction; means for decoding instructions from said memory means when said microcomputer is in said operation state and for outputting a power-save signal in response to said power-save instruction; signal outputting means connected to said decoding means and coupled to said externally-supplied interruption signal for outputting from said microcomputer to said at least one peripheral circuit a power-save mode signal in response to said power-save signal, said power-save mode signal indicating that said microcomputer is in said power-save state and said power-save mode signal continuing until said microcomputer receives said externally-supplied interruption signal; clock generating means for supplying timing signals to said microcomputer; clock control means connected to said clock generating means and to said decoder means for stopping all said timing signals to said microcomputer in response to said power-save signal and thereby placing said microcomputer in said power-save state; and input means connected to said signal outputting means for accepting an externally supplied power-save signal.

Claim 5

A microcomputer according to claim 2, in which said signal outputting means includes a flip-flop circuit having a set terminal coupled to said power save signal, and having a reset terminal coupled to said interruption signal.

Claim 6

A microcomputer according to claim 2, in which said signal outputting means includes a flip-flop circuit including means for setting by an external power-save signal and means for resetting by an external reset signal.