Patent US4590389A successfully refreshed from Google Patents.
US4590389A
Expired / Lapsed
US
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Compensation circuit and method for stabilization of a circuit node by multiplication of displacement current
Assignee: NXP USA Inc
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Filing: 1984-04-02
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Granted: 1986-05-20
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Expires: 2004-04-02
Abstract
Abstract A compensation circuit for stabilization of a circuit node coupled to an integrated circuit substrate by a parasitic capacitance of a value C 1 has a displacement current substantially equal to C 1 dv/dt. A switching device having a gain beta can either supply a current to, or draw a current from, the circuit node substantially equal to C 2 β dv/dt which is greater than the displacement current thereby obviating oscillation of an integrated circuit output due to capacitive coupling of the substrate to sensitive circuit nodes.
Inventors
- 👤 David L. Cave
- 👤 Byron G. Bynum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:47
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/14; H03K17/51; H03K17/56; H03K17/567
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
122 words
In an integrated circuit comprising a supply voltage line, a substrate of a first impurity type, an epitaxial region of a second impurity type and a circuit node in said epitaxial region, wherein the output is intended to be taken from said substrate and having parasitic capacitance between said substrate and said epitaxial region, the improvement comprising a compensation circuit which comprises a switching device having first, second and control terminals thereof, said first terminal being coupled to said supply voltage line, said control terminal being coupled to said substrate by said parasitic capacitance and said second terminal thereof being connected to said circuit node, said switching device for supplying a current to said circuit node being sufficient to prevent unwanted oscillations.
Claim 2
Dependent Claim
122 words
In an integrated circuit comprising a supply voltage line, a substrate of a first impurity type, an epitaxial region of a second impurity type and a circuit node in said epitaxial region, wherein the output is intended to be taken from said substrate and having parasitic capacitance between said substrate and said epitaxial region, the improvement comprising a compensation circuit which comprises a switching device having first, second and control terminals thereof, said first terminal being coupled to said supply voltage line, said control terminal being coupled to said substrate by said parasitic capacitance and said second terminal thereof being connected to said circuit node, said switching device for supplying a current to said circuit node being sufficient to prevent unwanted oscillations.
Claim 3
Dependent Claim
40 words
The compensation circuit of claim 1 further comprising: a diode having anode and cathode terminals thereof, said cathode terminal being coupled to said supply voltage line and said anode terminal being connected to said control terminal of said switching device.
Claim 4
Dependent Claim
30 words
The compensation circuit of claim 2 wherein said diode comprises an NPN bipolar transistor having an emitter as said cathode and a common connected base and collector as said anode.
Claim 5
Dependent Claim
15 words
The compensation circuit of claim 1 wherein said switching device is a PNP bipolar transistor.
Claim 6
Dependent Claim
25 words
The compensation circuit of claim 1 wherein said first, control and second terminals of said switching device are a emitter, base, and collector terminal respectively.
Claim 7
Independent Claim
117 words
A method for stabilization of a circuit node coupled to an integrated circuit substrate by a parasitic capacitance of a value C 1 and having a displacement current to said substrate substantially equal to C 1 dv/dt comprising: providing a switching device having a gain β and first, second and third terminals thereof; firstly coupling said first terminal to a supply voltage line; secondly coupling said second terminal to said substrate by a parasitic capacitance of a value C 2 ; connecting said third terminal to said circuit node; and supplying by means of said switching device a current to said circuit node substantially equal to C 2 β dv/dt which is greater than said displacement current.
Claim 8
Independent Claim
117 words
A method for stabilization of a circuit node coupled to an integrated circuit substrate by a parasitic capacitance of a value C 1 and having a displacement current to said substrate substantially equal to C 1 dv/dt comprising: providing a switching device having a gain β and first, second and third terminals thereof; firstly coupling said first terminal to a supply voltage line; secondly coupling said second terminal to said substrate by a parasitic capacitance of a value C 2 ; connecting said third terminal to said circuit node; and supplying by means of said switching device a current to said circuit node substantially equal to C 2 β dv/dt which is greater than said displacement current.
Claim 9
Dependent Claim
47 words
The method of claim 6 further comprising the step of: shunting said switching device by means of a diode having anode and cathode terminals thereof, said cathode being coupled to said supply voltage line and said anode being connected to said second terminal of said switching device.
Claim 10
Dependent Claim
36 words
The method of claim 7 wherein said step of shunting is carried out by means of an NPN bipolar transistor having an emitter as said cathode and a common connected base and collector as said anode.
Claim 11
Dependent Claim
20 words
The method of claim 6 wherein said step of providing is carried out by means of a PNP bipolar transistor.
Claim 12
Dependent Claim
147 words
In an integrated circuit comprising a supply voltage line, a substrate of a first impurity type, an epitaxial region of a second impurity type and a circuit node in said epitaxial region wherein the output is intended to be taken from said substrate and having parasitic capacitance between said substrate and said epitaxial region, the improvement comprising a compensation circuit which comprises: a switching device having first, second and control terminals thereof, said first terminal being coupled to said circuit node and said second and control terminals being coupled to said substrate by said parasitic capacitance; and a diode having anode and cathode terminals thereof, said cathode terminal being coupled to said supply voltage line and said anode being connected to said second and control terminals of said switching device, said switching device for drawing a current from said circuit node being sufficient to prevent unwanted oscillations.
Claim 13
Dependent Claim
147 words
In an integrated circuit comprising a supply voltage line, a substrate of a first impurity type, an epitaxial region of a second impurity type and a circuit node in said epitaxial region wherein the output is intended to be taken from said substrate and having parasitic capacitance between said substrate and said epitaxial region, the improvement comprising a compensation circuit which comprises: a switching device having first, second and control terminals thereof, said first terminal being coupled to said circuit node and said second and control terminals being coupled to said substrate by said parasitic capacitance; and a diode having anode and cathode terminals thereof, said cathode terminal being coupled to said supply voltage line and said anode being connected to said second and control terminals of said switching device, said switching device for drawing a current from said circuit node being sufficient to prevent unwanted oscillations.
Claim 14
Dependent Claim
30 words
The composition circuit of claim 10 wherein said diode comprises a NPN bipolar transistor having an emitter as said cathode and a common connected base and collector as said anode.
Claim 15
Dependent Claim
15 words
The compensation circuit of claim 10 wherein said switching device comprises a bipolar PNP transistor.
Claim 16
Dependent Claim
25 words
The compensation circuit of claim 10 wherein said first, control and second terminals of said switching device are a emitter, base and collector terminal respectively.
Claim 17
Independent Claim
140 words
A method for stabilization of a circuit node coupled to an integrated circuit substrate by parasitic capacitance of a value C 1 and having a displacement current to said substrate substantially equal to C 1 dv/dt comprising: providing a switching device having a gain β and first, second and third terminals thereof; connecting said first terminal to said circuit node; coupling said second and third terminals to said substrate by a parasitic capacitance of a value C 2 ; furnishing a diode having anode and cathode terminals thereof, said cathode being coupled to a supply voltage line and said anode being connected to said second and third terminals of said switching device; and drawing by means of said switching device a current from said circuit node substantially equal to C 2 β dv/dt which is greater than said displacement current.
Claim 18
Independent Claim
140 words
A method for stabilization of a circuit node coupled to an integrated circuit substrate by parasitic capacitance of a value C 1 and having a displacement current to said substrate substantially equal to C 1 dv/dt comprising: providing a switching device having a gain β and first, second and third terminals thereof; connecting said first terminal to said circuit node; coupling said second and third terminals to said substrate by a parasitic capacitance of a value C 2 ; furnishing a diode having anode and cathode terminals thereof, said cathode being coupled to a supply voltage line and said anode being connected to said second and third terminals of said switching device; and drawing by means of said switching device a current from said circuit node substantially equal to C 2 β dv/dt which is greater than said displacement current.
Claim 19
Dependent Claim
36 words
The method of claim 14 wherein said step of furnishing is carried out by means of an NPN bipolar transistor having an emitter as said cathode and a common connected base and collector as said anode.
Claim 20
Dependent Claim
20 words
The method of claim 14 wherein said step of providing is carried out by means of a PNP bipolar transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-19 | 1989-11-18 | 1990-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-19 | 1993-11-18 | 1994-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-19 | 1997-11-18 | 1998-05-20 | $7700.00 | Window Closed / Lapsed |