CMOS FET device with abnormal current flow prevention

Claim 1

In an integrated semiconductor circuit biased by a power source and including a CMOS FET device which comprises a first region of one conductivity type; a second region of the opposite conductivity type formed in the first region; a one channel type MOS transistor formed in that portion of the first region which lies outside of the second region; and an MOS transistor of the opposite channel type provided in the second region, said MOS transistors each having a source and a drain, said power source being selectively coupled in step fashion to one of said sources and drains and to the region in which said one of said sources and drains is formed to bias said CMOS FET device, said device including a potential thyristor circuit formed of parasitic bipolar transistors with one of said parasitic bipolar transistors including said one of said sources and drains, said thyristor circuit establishing current flow from said power source through said first and second regions upon application of said power source due to biasing as a result of a delay before said region in which said one source and drain is formed reaches the full potential of said power source, the improvement comprising: capacitor means for delaying the rise in potential of said one source and drain upon application of said power source enough to reduce the instantaneous difference between the potential of said one source and drain and the potential of said one region sufficient to prevent conduction of said one of said parasitic bipolar transistors, said capacitor means being coupled in parallel to said power source and said capacitor means also being provided to absorb impulse noise signals acting as a trigger pulse for said thyristor circuit.