Patent US4588941A successfully refreshed from Google Patents.
US4588941A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cascode CMOS bandgap reference
Assignee: Nokia Bell Labs
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Filing: 1985-02-11
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Granted: 1986-05-13
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Expires: 2005-02-11
Abstract
Abstract A CMOS bandgap voltage reference which is temperature stable is disclosed. The large temperature-dependent p-tub resistors of prior art arrangements are replaced with relatively small, temperature stable p+ diffusion resistors. The increase in current level needed to compensate for the decrease in resistor value is provided by a simple cascode MOS circuit located between the ratioing resistors and the VSS potential.
Inventors
- 👤 Donald A. Kerth
- 👤 Navdeep S. Sooch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:33
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/30; Y; Y10; Y10S; Y10S323/00; Y10S323/907
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
328 words
A voltage reference circuit for providing as an output a bandgap reference voltage which is substantially independent of temperature, said reference circuit comprising differential amplifying means including a first and a second input terminal and an output terminal; a first bipolar transistor including a collector, a base, and an emitter, the collector and base connected to a first reference potential, said first bipolar transistor having a base to emitter voltage defined as V BE ; a second bipolar transistor including a collector, a base, and an emitter, the collector and base connected to said first reference potential and the emitter connected to said first input terminal of said differential amplifying means; a first resistor connected between the emitter of said first transistor and said second input terminal of said differential amplifying means; a second resistor connected to the emitter of said second bipolar transistor; and an MOS cascode transistor arrangement connected in series between said first and second resistors and a second reference potential and further connected to the output terminal of said differential amplifying means, said MOS cascode transistor arrangement including a first plurality of MOS transistors, each MOS transistor having a source, drain and gate terminal and formed to comprise a width-to-length ratio defined as Z/L, said first plurality of MOS transistors connected between said first resistor and said second reference potential; and a second plurality of MOS transistors, each MOS transistor having a source, drain and gate terminal and formed to comprise a width-to-length ratio defined as n(Z/L), n being defined as a width-to-length size factor, said second plurality of MOS transistors connected between said second resistor and said second reference potential, said MOS cascode transistor arrangement providing the output bandgap reference voltage which is proportional to the sum of said base-to-emitter voltage of said first transistor and the ratio of said second and first resistors multiplied by both said size factor n and the difference in base-to-emitter voltages of said first and second transistors.
Claim 2
Dependent Claim
328 words
A voltage reference circuit for providing as an output a bandgap reference voltage which is substantially independent of temperature, said reference circuit comprising differential amplifying means including a first and a second input terminal and an output terminal; a first bipolar transistor including a collector, a base, and an emitter, the collector and base connected to a first reference potential, said first bipolar transistor having a base to emitter voltage defined as V BE ; a second bipolar transistor including a collector, a base, and an emitter, the collector and base connected to said first reference potential and the emitter connected to said first input terminal of said differential amplifying means; a first resistor connected between the emitter of said first transistor and said second input terminal of said differential amplifying means; a second resistor connected to the emitter of said second bipolar transistor; and an MOS cascode transistor arrangement connected in series between said first and second resistors and a second reference potential and further connected to the output terminal of said differential amplifying means, said MOS cascode transistor arrangement including a first plurality of MOS transistors, each MOS transistor having a source, drain and gate terminal and formed to comprise a width-to-length ratio defined as Z/L, said first plurality of MOS transistors connected between said first resistor and said second reference potential; and a second plurality of MOS transistors, each MOS transistor having a source, drain and gate terminal and formed to comprise a width-to-length ratio defined as n(Z/L), n being defined as a width-to-length size factor, said second plurality of MOS transistors connected between said second resistor and said second reference potential, said MOS cascode transistor arrangement providing the output bandgap reference voltage which is proportional to the sum of said base-to-emitter voltage of said first transistor and the ratio of said second and first resistors multiplied by both said size factor n and the difference in base-to-emitter voltages of said first and second transistors.
Claim 3
Dependent Claim
153 words
A voltage reference circuit as defined in claim 1 wherein the MOS cascode transistor arrangement comprises a first and a second MOS transistor, forming the first plurality of MOS transistors, connected in series between the first resistor and the second reference potential, wherein the gate terminal of the first MOS transistor is connected to the output of the differential amplifying means and the gate of the second MOS transistor is connected to the interconnection of the source of the first MOS transistor and the drain of the second MOS transistor; and a third and a fourth MOS transistor, forming the second plurality of MOS transistors, connected in series between the second resistor and the second reference potential, wherein the gate terminal of said third transistor is connected to the gate terminal of said first transistor and the gate terminal of said fourth transistor is connected to the gate terminal of said second transistor.
Claim 4
Dependent Claim
104 words
A voltage reference circuit as defined in claim 2 wherein said circuit further comprises a fifth MOS transistor including a source, drain and gate for providing a reference current, the gate of said fifth MOS transistor connected to the interconnected gates of the second and fourth MOS transistors and the source of said fifth transistor connected to the second reference potential, said fifth MOS transistor comprising a width-to-length ratio of m(Z/L) and providing a drain currents as the output reference current related to the ratio of m and the first resistor multiplied by a constant value related to the first and second bipolar transistors.
Claim 5
Dependent Claim
58 words
A voltage reference circuit as defined in claim 2 wherein said circuit further comprises an MOS cascode current mirror disposed between the first and second reference potentials and connected to the cascode MOS transistor arrangement for biasing said cascode MOS transistor arrangement at a predetermined value which decreases the voltage difference between said first and second reference potentials.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-12 | 1989-11-11 | 1990-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-12 | 1993-11-11 | 1994-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-12 | 1997-11-11 | 1998-05-13 | $7700.00 | Window Closed / Lapsed |