Bandgap reference

Claim 2

A reference voltage circuit comprising: first and second common-collector amplifier transistors of the same conductivity type having respective base electrodes respectively connected to a first node, having respective emitter electrodes and respective base-emitter junctions; first, second and third resistive means each having a respective first end and a respective second end; the first ends of said first and second resistive means connected to a common potential, the second ends of said first and third resistive means connected to the respective emitter electrodes of the first and second transistor respectively, and the first end of the third resistive means connected at the second end of the second resistive means; a differential-input amplifier having inverting and non-inverting input connections connected for receiving respective potentials from the second ends of said first and second resistive means, and having an output connection, said differential input amplifier for providing at its output connection an amplified response to a potential difference across its input connections; and means connecting the output connection of the differential-input amplifier to the first node to complete a direct coupled feedback loop, said feedback loop functioning to condition said first and second transistors to maintain the density of current in their base-emitter junctions in a prescribed ratio.

Claim 3

A reference voltage circuit comprising: a common-collector amplifier transistor having a base electrode connected to a first node, having first and second emitter electrodes and first and second base-emitter junctions; first, second and third resistive means each having a respective first and second end, the first ends of said first and second resistive means connected to a common potential, the second ends of said first and third resistive means connected to the first and second emitter electrodes respectively, and the first end of the third resistive means connected at the second end of the second resistive means; a differential-input amplifier having inverting and non-inverting input connections connected for receiving respective potentials from the second ends of said first and second resistive means, and having an output connection, said differential-input amplifier for providing at its output connection an amplified response to a potential difference across its input connection; and means connecting the output connection of the differential-input amplifier to the first node to complete a direct coupled feedback loop, said feedback loop functioning to condition said transistor to maintain the density of current in the first and second base-emitter junctions in a prescribed ratio.

Claim 4

A reference voltage circuit comprising: a common-collector amplifier transistor having a base electrode connected to a first node, having first and second emitter electrodes and first and second base-emitter junctions; first, second and third resistive means each having a respective first and second end, the first ends of said first and second resistive means connected to a common potential, the second ends of said first and third resistive means connected to the first and second emitter electrodes respectively, and the first end of the third resistive means connected at the second end of the second resistive means; a differential-input amplifier having inverting and non-inverting input connections connected for receiving respective potentials from the second ends of said first and second resistive means, and having an output connection, said differential-input amplifier for providing at its output connection an amplified response to a potential difference across its input connection; and means connecting the output connection of the differential-input amplifier to the first node to complete a direct coupled feedback loop, said feedback loop functioning to condition said transistor to maintain the density of current in the first and second base-emitter junctions in a prescribed ratio.

Claim 5

A reference voltage circuit comprising: a CMOS integrated circuit formed in a monolithic substrate having first and second parasitic bipolar transistors each having respective collector regions common to the monolithic substrate material, having respective base regions formed by wells of opposite conductivity type material to the substrate disposed in the surface of substrate, having emitter regions of like conductivity type to the substrate disposed at the surface of said wells with base-emitter junctions therebetween and respective collector, base and emitter electrodes for making ohmic contact to the respective collector, base and emitter regions respectively, the first and second transistors connected as common-collector amplifiers with their respective base electrodes connected to a first node; first, second and third resistive means each having a respective first end and a respective second end; the first ends of said first and second resistive means connected to a common potential, the second ends of said first and third resistive means connected to the respective emitter electrodes of the first and second transistors respectively, and the first end of the third resistive means connected at the second end of the second resistive means; a differential-input amplifier having inverting and non-inverting input connections connected for receiving respective potentials from the second ends of said first and second resistive means, and having an output connection, said differential input amplifier for providing at its output connection an amplified response to a potential difference across its input connections; and means connecting the output connection of the differential-input amplifier to the first node to complete a direct coupled feedback loop, said feedback loop functioning to condition said first and second transistors to maintain the density of current in their base-emitter junctions in a prescribed ratio.

Claim 6

A reference voltage circuit comprising: a CMOS integrated circuit formed in a monolithic substrate having first and second parasitic bipolar transistors each having respective collector regions common to the monolithic substrate material, having respective base regions formed by wells of opposite conductivity type material to the substrate disposed in the surface of substrate, having emitter regions of like conductivity type to the substrate disposed at the surface of said wells with base-emitter junctions therebetween and respective collector, base and emitter electrodes for making ohmic contact to the respective collector, base and emitter regions respectively, the first and second transistors connected as common-collector amplifiers with their respective base electrodes connected to a first node; first, second and third resistive means each having a respective first end and a respective second end; the first ends of said first and second resistive means connected to a common potential, the second ends of said first and third resistive means connected to the respective emitter electrodes of the first and second transistors respectively, and the first end of the third resistive means connected at the second end of the second resistive means; a differential-input amplifier having inverting and non-inverting input connections connected for receiving respective potentials from the second ends of said first and second resistive means, and having an output connection, said differential input amplifier for providing at its output connection an amplified response to a potential difference across its input connections; and means connecting the output connection of the differential-input amplifier to the first node to complete a direct coupled feedback loop, said feedback loop functioning to condition said first and second transistors to maintain the density of current in their base-emitter junctions in a prescribed ratio.

Claim 7

A reference voltage circuit as set forth in claim 1, wherein the resistances of the second and third resistive means are chosen in such ratio that a substantially zero-temperature coefficient voltage is maintained at said first node.

Claim 8

A reference voltage circuit as set forth in claims 1, 2 or 3 wherein the means connecting the output connection of the differential input amplifier to the first node comprises a direct connection without substantial intervening impedance.

Claim 9

A voltage reference circuit as set forth in claims 1, 2 or 3 wherein the means connecting the output connection of the differential-input amplifier to the first node comprises a resistor-divider circuit connected between the amplifier output connection and the common potential, said resistor-divider having an output terminal connected to said first node to apply a portion of the potential available from said amplifier thereto.

Claim 10

A reference voltage circuit as set forth in claims 1, 2 or 3 wherein said means connecting the output connection of the differential input amplifier to the first node comprises fourth resistive means; and wherein said reference voltage circuit further comprises: further amplifier means having an input connection at the non-inverting input connection of the differential-input amplifier and having an output connection, said further amplifier means exhibiting a substantially unity-gain, non-inverting transfer function; fifth resistive means connected between the first node and the output connection of the further amplifier means; and means connected to the output connection of the differential-input amplifier from which a substantially temperature insensitive voltage is available including: sixth resistive means having a first end connected to the common potential and having a second end at which point the temperature insensitive voltage is available; and a pn junction having voltage-temperature characteristics and forward offset potential similar to the base-emitter junction of the first transistor, having a first end connected at said amplifier output connection and having a second end connected at the second end of the sixth resistor, said pn junction being poled to be normally forward conducting.

Claim 11

A reference voltage circuit as set forth in claim 7 wherein: the forward potential of the base-emitter junction serially connected with the first resistive means is V BE ; a difference in forward base-emitter junction potentials due to the prescribed ratio of current densities is ΔV BE ; the resistance values of the second, third, fourth, fifth and sixth resistive means are respectively R2, R3, R4, R5, R6; the ratio of R4:R5 is equal to ##EQU3## and the substantially temperature insensitive output voltage E ref is given by ##EQU4## .