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US4586091A
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System and method for high density data recording
Assignee: Kalhas Oracle Inc
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Filing: 1984-05-03
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Granted: 1986-04-29
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Expires: 2004-05-03
Abstract
Abstract A method and system for high density data recording is provided. Parallel encoded digital data are converted to corresponding serial format data words. Individual cycles of a periodic signal are selectively attenuated in accordance with the logic state of individual bits of the serial data words. By determining the relative level of the periodic signal during periods defined by individual cycles of the signal, the sequence of logic data bits forming the serial data words can be reconstructed.
Inventors
- 👤 Spyro Panaoussis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:06
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
119 words
A system for processing digitally encoded data for storage on a magnetic recording medium, comprising: clock signal means for generating a periodic clock signal of substantially constant frequency; data signal means operable from said clock signal for generating a periodic data signal of substantially constant frequency; data conversion means responsive to said clock signal for converting the parallel digitally encoded data to a corresponding plurality of sequentially occurring bi-stable logic bits; and signal attenuation means responsive to said plurality of sequentially occurring logic bits for attenuating said data signal in accordance with the logic state of each of said bits, whereby, the logic state of each of said bits is indicated by the relative level of said data signal.
Claim 2
Independent Claim
119 words
A system for processing digitally encoded data for storage on a magnetic recording medium, comprising: clock signal means for generating a periodic clock signal of substantially constant frequency; data signal means operable from said clock signal for generating a periodic data signal of substantially constant frequency; data conversion means responsive to said clock signal for converting the parallel digitally encoded data to a corresponding plurality of sequentially occurring bi-stable logic bits; and signal attenuation means responsive to said plurality of sequentially occurring logic bits for attenuating said data signal in accordance with the logic state of each of said bits, whereby, the logic state of each of said bits is indicated by the relative level of said data signal.
Claim 3
Dependent Claim
19 words
A system as defined in claim 1 wherein said data and said clock signals are of the same frequency.
Claim 4
Dependent Claim
23 words
A system as defined in claim 2 wherein said data conversion means provide a single bit during each cycle of said clock signal.
Claim 5
Dependent Claim
20 words
A system as defined in claim 3 wherein said data and said clock signals each comprise substantially sinusoidal periodic signals.
Claim 6
Dependent Claim
26 words
A system as defined in claim 4 wherein the level of said clock and data signals is limited as to avoid saturating the magnetic recording medium.
Claim 7
Dependent Claim
24 words
A system as defined in claim 5 wherein said clock and said data signals are recorded on separate channels of the magnetic recording medium.
Claim 8
Dependent Claim
25 words
A system as defined in claim 5 wherein said clock and said data signals are recorded on the same channel on the magnetic recording medium.
Claim 9
Dependent Claim
31 words
A system as defined in claim 6 wherein said signal attenuation means fully attenuate said data signal in accordance with the logic state of said bits of the digitally encoded data.
Claim 10
Dependent Claim
31 words
A system as defined in claim 7 wherein said signal attenuation means partially attenuate said data signal in accordance with the logic state of said bits of the digitally encoded data.
Claim 11
Dependent Claim
34 words
A system as defined in claim 8 wherein the digitally encoded data are applied to said system in the form of parallel data bytes, each of the bytes comprising a fixed number of bits.
Claim 12
Dependent Claim
34 words
A system as defined in claim 9 wherein the digitally encoded data are applied to said system in the form of parallel data bytes, each of the bytes comprising a fixed number of bits.
Claim 13
Dependent Claim
22 words
A system as defined in claim 10 wherein said data conversion means comprise a Parallel-In/Serial-Out shift register operable from said clock signal.
Claim 14
Dependent Claim
22 words
A system as defined in claim 11 wherein said data conversion means comprise a Parallel-In/Serial-Out shift register operable from said clock signal.
Claim 15
Independent Claim
111 words
A method for processing parallel digitally encoded data comprising the steps of: generating a periodic clock signal of substantially constant frequency; generating a periodic data signal of substantially constant frequency; converting the parallel digitally encoded data to a plurality of sequentially occurring bi-stable logic data bits, each of said bits being produced upon the occurrence of a fixed number of cycles of said clock signal; and attenuating selected cycles of said data signal in accordance with the logic state of individual ones of said plurality of logic bites, whereby the level of individual cycles of said data signal indicate the logic state of respective ones of said plurality of logic bits.
Claim 16
Independent Claim
111 words
A method for processing parallel digitally encoded data comprising the steps of: generating a periodic clock signal of substantially constant frequency; generating a periodic data signal of substantially constant frequency; converting the parallel digitally encoded data to a plurality of sequentially occurring bi-stable logic data bits, each of said bits being produced upon the occurrence of a fixed number of cycles of said clock signal; and attenuating selected cycles of said data signal in accordance with the logic state of individual ones of said plurality of logic bites, whereby the level of individual cycles of said data signal indicate the logic state of respective ones of said plurality of logic bits.
Claim 17
Dependent Claim
20 words
A method as defined in claim 14 wherein said clock signal and said data signal operate at the same frequency.
Claim 18
Dependent Claim
23 words
A method as defined in claim 15 each said logic data bit is provided in response to one cycle of said clock signal.
Claim 19
Dependent Claim
22 words
A method as defined in claim 16 wherein said clock and data signals each comprise periodic substantially sinusoidal signals of constant frequency.
Claim 20
Dependent Claim
39 words
A method as defined in claim 17 wherein said data signal is partially attenuated in response to said logic data bits being of one state and unattenuated in response to said logic data bits being of opposite logic state.
Claim 21
Dependent Claim
39 words
A method as defined in claim 17 wherein said data signal is fully attenuated in response to said logic data bits being of one state and unattenuated in response to said logic data bits being of opposite logic state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-28 | 1989-10-28 | 1990-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-28 | 1993-10-28 | 1994-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-28 | 1997-10-28 | 1998-04-29 | $7700.00 | Window Closed / Lapsed |