US3736581A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density digital recording
Assignee: Honeywell Inc
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Filing: 1971-07-02
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Granted: 1973-05-29
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Expires: 1991-07-02
Abstract
Abstract A playback system for a high density digital recording carrying digital information in the form of a code composed of pulse lengths between successive zero crossings. Random variations in these pulse lengths after playback of the recorded information are compensated by converting the duration of the pulse lengths into counts of a fixed clock and, subsequently, decoding the count data into binary form by sensing a first plurality of counts for one type of binary data and a second plurality of counts for a second type of binary data. The two types of binary data are temporarily stored in respective flip-flop circuit between successive decoding operations controlled by a clock signal derived from a frequency multiplication of the input signals.
Inventors
- 👤 I Breikss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:27
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
146 words
A playback system comprising: input terminals means arranged to be connected to a source of digital input signals, clock means for producing a constant frequency clock signal having a frequency higher than the highest frequency of said digital input signals, NAND gate means having a first input connected to said input terminals and a second input connected to said clock means, said NAND gate means being arranged to selectively route said clock signals to an output of said gate means in response to said input signals, counter means connected to said output of said gate means to count said clock signals, and decoder means connected to said counter means and arranged to provide a first output signal representative of a first plurality of counts stored in said counter means and a second output signal representative of a second plurality of counts stored in said counter means.
Claim 2
Dependent Claim
146 words
A playback system comprising: input terminals means arranged to be connected to a source of digital input signals, clock means for producing a constant frequency clock signal having a frequency higher than the highest frequency of said digital input signals, NAND gate means having a first input connected to said input terminals and a second input connected to said clock means, said NAND gate means being arranged to selectively route said clock signals to an output of said gate means in response to said input signals, counter means connected to said output of said gate means to count said clock signals, and decoder means connected to said counter means and arranged to provide a first output signal representative of a first plurality of counts stored in said counter means and a second output signal representative of a second plurality of counts stored in said counter means.
Claim 3
Dependent Claim
33 words
A playback system as set forth in claim 1 wherein said gate means includes means for summing said input signal with said clock signals to provide an output signal from said gate means.
Claim 4
Dependent Claim
34 words
A playback system as set forth in claim 1 wherein said decoder means includes a first-flop means for storing said first output signal and a second flip-flop means for storing said second output signal.
Claim 5
Dependent Claim
30 words
A playback system as set forth in claim 1 wherein said first plurality of counts encompasses a + or - 32 percent range with respect to a predetermined medial count.
Claim 6
Dependent Claim
31 words
A playback system as set forth in claim 4 wherein said second plurality of counts encompaSses a + or - 32 percent range with respect to a second predetermined medial count.
Claim 7
Dependent Claim
144 words
A playback system as set forth in claim 1 and including a second NAND gate means having a first input and a second input, said second input being connected to said clock means, logical inverter means connected between said input terminals and said first input of said second NAND gate means, said second NAND gate means being arranged to selectively route said clock signals to an output of said gate means in response to said input signals, second counter means connected to an output of said second NAND gate means to count said clock signals, and second decoder means connected to said second counter means and arranged to provide a first output signal representative of a first plurality of counts stored in said second counter means and a second output signal representative of a second plurality of counts stored in said second counter means.
Claim 8
Dependent Claim
59 words
A playback system as set forth in claim 6 wherein said second decoder means includes means to reset said first-mentioned counter means upon the attainment of a predetermined count by said second counter means and said first-mentioned decoder means includes means to reset said second counter means upon the attainment of a predetermined count in said first-mentioned counter means.
Claim 9
Dependent Claim
40 words
A playback system as set forth in claim 7 wherein said second NAND gate means includes means for summing an output signal from said inverter means with said clock signals to produce an output signal from said second gate means.
Claim 10
Dependent Claim
49 words
A playback system as set forth in claim 6 wherein said decoder means includes a first flip-flop means for storing said first output signal from said first or second decoder means and a second flip-flop means for storing said second output signal from said first or second decoder means.
Claim 11
Dependent Claim
36 words
A playback system as set forth in claim 6 wherein said first-mentioned and said second-mentioned first and second plurality of counts encompasses a + or - 32 percent range with respect to a predetermined medial count.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-28 | 1976-11-27 | 1977-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-28 | 1980-11-27 | 1981-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-28 | 1984-11-27 | 1985-05-29 | $7700.00 | Window Closed / Lapsed |