US4584660A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reduction of series propagation delay and impedance
Assignee: Intersil Corp
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Filing: 1983-06-22
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Granted: 1986-04-22
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Expires: 2003-06-22
Abstract
Abstract A serial fast propagation transmission switch responsive to a propagate input control signal to transmit a signal from the input to the output terminal in combination with a double inverting logic parallel to the transmission switch to limit the line impedance to a single stage impedance subsequent to the serial transmission.
Inventors
- 👤 William R. Young
- 👤 Michael C. Hoke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:36
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5055; G06F7/501; G06F7/503; G06F7/506; G06F7/508; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3872
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
95 words
A propagation circuit comprising: an input signal terminal; an output signal terminal; a propagate input terminal; a transmission means connected in series between said input signal and output signal terminals for transmitting an input signal at said input signal terminal to said output signal terminal without delay in response to a propagate signal on said propagate input terminal; and limiting means connected to said input signal terminal for limiting the series impedance of said propagation circuit subsequent to transmission by said transmission means in response to a low input signal at said input signal terminal.
Claim 2
Dependent Claim
95 words
A propagation circuit comprising: an input signal terminal; an output signal terminal; a propagate input terminal; a transmission means connected in series between said input signal and output signal terminals for transmitting an input signal at said input signal terminal to said output signal terminal without delay in response to a propagate signal on said propagate input terminal; and limiting means connected to said input signal terminal for limiting the series impedance of said propagation circuit subsequent to transmission by said transmission means in response to a low input signal at said input signal terminal.
Claim 3
Dependent Claim
40 words
A circuit according to claim 1 including logic high means connected to said output signal terminal for producing a logic high signal at said output signal terminal in response to a logic low propagate signal at said propagate input terminal.
Claim 4
Dependent Claim
48 words
A circuit according to claim 2 wherein said limiting means includes logic low means connected to said input signal terminal for maintaining a logic low signal distinct from said input signal at said output signal terminal in response to a logic low signal at said input signal terminal.
Claim 5
Dependent Claim
48 words
A circuit according to claim 1 wherein said limiting means includes logic low means connected to said input signal terminal for maintaining a logic low signal distinct from said input signal at said output signal terminal in response to a logic low signal at said input signal terminal.
Claim 6
Dependent Claim
63 words
A circuit according to claim 4 wherein said logic low means includes an inverter means having an input connected to said input signal terminal and an output and a latch means having an input connected to said output of said inverter means for latching said input signal terminal to a logic low in response to a logic low at said input signal terminal.
Claim 7
Dependent Claim
62 words
A circuit according to claim 1 wherein said limiting means includes an inverter means having an input connected to said input signal terminal and an output and a latch means having an input connected to said output of said inverter means for latching said input signal terminal to a logic low in response to a logic low at said input signal terminal.
Claim 8
Dependent Claim
125 words
A carry circuit comprising: a carry-in input terminal; a carry-out output terminal; a propagate input terminal. a generate input terminal; a generate means connected to said carry-out output terminal for producing a logic low on said carry-out output terminal in response to a generate signal at said generate input terminal; a transmission means connected in series between said carry-in and said carry-out terminals for transmitting a carry-in signal at said carry-in input terminal to said carry-out terminal without delay in response to a propagate signal on said propagate input terminal; and limiting means connected to said carry-in terminal for limiting the series impedance of said carry circuit subsequent to tranmission by said transmission means in response to a low carry-in signal at said carry-in terminal.
Claim 9
Dependent Claim
125 words
A carry circuit comprising: a carry-in input terminal; a carry-out output terminal; a propagate input terminal. a generate input terminal; a generate means connected to said carry-out output terminal for producing a logic low on said carry-out output terminal in response to a generate signal at said generate input terminal; a transmission means connected in series between said carry-in and said carry-out terminals for transmitting a carry-in signal at said carry-in input terminal to said carry-out terminal without delay in response to a propagate signal on said propagate input terminal; and limiting means connected to said carry-in terminal for limiting the series impedance of said carry circuit subsequent to tranmission by said transmission means in response to a low carry-in signal at said carry-in terminal.
Claim 10
Dependent Claim
46 words
A carry circuit according to claim 7 including logic high means connected to said carry-out terminal for producing a logic high signal at said carry-out terminal in response to a low propagate signal and a low generate signal at said propagate and generate input terminals respectively.
Claim 11
Dependent Claim
46 words
A carry circuit according to claim 8 wherein said limiting means includes logic low means connected to said carry-in terminal for maintaining a logic low signal distinct from said carry-in signal at said carry-out terminal in response to a logic low signal at said carry-in terminal.
Claim 12
Dependent Claim
55 words
A carry circuit according to claim 7 including a logic high means connected to said carry-out terminal for producing a logic high signal at said carry-out terminal in response to a logic low generate signal and either a logic low propagate or a logic high carry-in signal at said generate, propagate and carry-in terminals respectively.
Claim 13
Dependent Claim
46 words
A carry circuit according to claim 7 wherein said limiting means includes logic low means connected to said carry-in terminal for maintaining a logic low signal distinct from said carry-in signal at said carry-out terminal in response to a logic low signal at said carry-in terminal.
Claim 14
Dependent Claim
42 words
A carry circuit according to claim 11 wherein said logic low means is responsive to a logic low carry-in signal and logic high propagate signal at said carry-in and propagate input terminals respectively to maintain a logic low at said carry-out terminal.
Claim 15
Dependent Claim
54 words
A carry circuit according to claim 12 including a logic high means connected to said carry-out terminal for producing a logic high signal at said carry-out terminal in response to a logic low generate signal and either a logic low propagate or logic high carry-in signal at said generate, propagate and carryin terminals respectively.
Claim 16
Dependent Claim
61 words
A carry circuit according to claim 7 wherein said limiting means includes an inverter means having an input connected to said carry-in terminal and an output and a latch means having an input connected to said output of said inverter means for latching said carry-out terminal to a logic low in response to a logic low at said carry-in input terminal.
Claim 17
Dependent Claim
40 words
A carry circuit according to claim 7 including a logic low means connected to said carry-out terminal for producing a logic low signal at said output terminal in response to a logic high generate signal at said generate input terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-21 | 1989-10-21 | 1990-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-21 | 1993-10-21 | 1994-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-21 | 1997-10-21 | 1998-04-22 | $7700.00 | Window Closed / Lapsed |