Semiconductor device of non-single crystal structure

Claim 2

A semiconductor device comprising: a substrate and a non-single crystal semiconductor layer formed on or over the substrate, the non-single crystal semiconductor layer being composed of a first semiconductor region formed primarily of a first semi-amorphous semiconductor and a second semiconductor region (a) formed primarily of a second semi-amorphous semiconductor containing microcrystalline semiconductor more than the first semi-amorphous semiconductor and (b) having a higher degree of conductivity than the first semiconductor region; wherein the first and second semiconductor regions are laterally arranged side by side on or over the substrate.

Claim 3

A semiconductor device according to claim 1, which further comprises a first conductive layer extending between the substrate and the second semiconductor region and a second conductive layer extending on or over the second semiconductor region.

Claim 4

A semiconductor device according to claim 2 which further comprises a first insulating layer extending between the first conductive layer and the second semiconductor region and a second insulating layer extending between the second semiconductor region and the second conductive layer.

Claim 5

A semiconductor device according to claim 1, wherein the second semiconductor region is doped with an impurity which imparts thereto an N or P conductivity type.

Claim 6

A semiconductor device according to claim 1 where said non-single crystal semiconductor layer is further composed of a third semiconductor region (a) formed primarily of said second semi-amorphous semiconductor and where the first, second and third semiconductor regions are laterally arranged side by side on or over the substrate so that first semiconductor region is sandwiched between the second and third semiconductor regions.

Claim 7

A semiconductor device according to claim 5 wherein the second and third semiconductor regions are doped with an impurity which imparts thereto an N or P conductivity type.

Claim 8

A semiconductor device according to claim 6 further comprises an insulating layer extending on the first semiconductor region and a conductive layer extending on the insulating layer.

Claim 9

A semiconductor device according to claim 1 where said non-single crystal semiconductor layer is composed of a plurality of said first semiconductor regions where each is formed primarily of said first semi-amorphous semiconductor and a plurality of said second semiconductor regions where each is formed primarily of said second semi-amorphous semiconductor and where the first and second semiconductor regions are laterally arranged side by side on or over the substrate.

Claim 10

A semiconductor device according to claim 8 which further comprises a first conductive layer extending between the substrate and the non-single-crystal semiconductor layer.

Claim 11

A semiconductor device comprising: a plurality of photoelectric conversion elements formed on a substrate side by side; wherein the photoelectric conversion elements each has a first conductive layer as a first electrode formed on the substrate, a non-single-crystal semiconductor layer formed on the first conductive layer, formed of Si, Ge, Si3N 4-x (0<x<4), SiO 2x (0<x<2) or Si x Ge 1-x (0<x<1), or a material consisting principally thereof and doped with hydrogen or halogen as a dangling bond neutralizer, and a second conductive layer as a second electrode formed on the non-single-crystal semiconductor layer; wherein the second conductive layer of one of the photoelectric conversion elements is coupled with the first conductive layer of the next photoelectric conversion element; wherein the non-single-crystal semiconductor layers of the photoelectric conversion elements each has a first semiconductor region and a second semiconductor region having a higher degree of conductivity than the first semiconductor region; wherein the first and second semiconductor regions are laterally arranged side by side on the first conductive layer; and wherein the first semiconductor region is formed primarily of a first semiamorphous semiconductor, and wherein the second semiconductor region is formed primarily of a second semiamamorphous semiconductor containing more microcrystalline semiconductor than the first semiamorphous semiconductor.

Claim 12

A semiconductor device comprising: a plurality of photoelectric conversion elements formed on a substrate side by side; wherein the photoelectric conversion elements each has a first conductive layer as a first electrode formed on the substrate, a non-single-crystal semiconductor layer formed on the first conductive layer, formed of Si, Ge, Si3N 4-x (0<x<4), SiO 2x (0<x<2) or Si x Ge 1-x (0<x<1), or a material consisting principally thereof and doped with hydrogen or halogen as a dangling bond neutralizer, and a second conductive layer as a second electrode formed on the non-single-crystal semiconductor layer; wherein the second conductive layer of one of the photoelectric conversion elements is coupled with the first conductive layer of the next photoelectric conversion element; wherein the non-single-crystal semiconductor layers of the photoelectric conversion elements each has a first semiconductor region and a second semiconductor region having a higher degree of conductivity than the first semiconductor region; wherein the first and second semiconductor regions are laterally arranged side by side on the first conductive layer; and wherein the first semiconductor region is formed primarily of a first semiamorphous semiconductor, and wherein the second semiconductor region is formed primarily of a second semiamamorphous semiconductor containing more microcrystalline semiconductor than the first semiamorphous semiconductor.

Claim 13

A semiconductor device according to claim 10, which further comprises a first insulating layer extending between the first conductive layer and the second semiconductor region and a second insulating layer extending between the second semiconductor region and the second conductive layer.

Claim 14

A semiconductor device according to claim 10, wherein the second semiconductor region is doped with an impurity which imparts thereto an N or P conductive type.

Claim 15

A semiconductor device comprising: a plurality of MIS type transistors formed side by side on a substrate; wherein the MIS type transistors each has a non-single-crystal semiconductor layer formed on the substrate an insulating layer formed on the non-single-crystal semiconductor layer and a conductive layer formed on the insulating layer; wherein the non-single crystal semiconductor layer is formed of Si, Ge, Si 3 N 4-x (0<x<4), SiO 2-x (0<x<2), SiC x (0<x<1) or Si x Ge 1-x (0<x<1), or a material consisting principally thereof and doped with hydrogen or halogen as a dangling bond neutralizer; wherein the non-single-crystal semiconductor has a first semiconductor region as a channel region a second and third semiconductor regions as a source and drain regions respectively connected with the opposing sides of the first semiconductor regions, respectively and having a P or N conductivity type and having a higher degree of conductivity than the first region; wherein the third, first and second regions are laterally arranged side by side in this order on the substrate; wherein the insulating layer is disposed on at least the first semiconductor region as a gate insulating layer; wherein the conductive layer is disposed on at least the first semiconductor region through the insulating layer as a gate electrode; and wherein the first semiconductor region is formed primarily of a first semi-amorphous semiconductor, and wherein the second and third semiconductor regions are formed primarily of a second semi-amorphous semiconductor containing more microcrystalline semiconductor than the first semi-amorphous semiconductor.

Claim 16

A semiconductor device comprising: a plurality of MIS type transistors formed side by side on a substrate; wherein the MIS type transistors each has a non-single-crystal semiconductor layer formed on the substrate an insulating layer formed on the non-single-crystal semiconductor layer and a conductive layer formed on the insulating layer; wherein the non-single crystal semiconductor layer is formed of Si, Ge, Si 3 N 4-x (0<x<4), SiO 2-x (0<x<2), SiC x (0<x<1) or Si x Ge 1-x (0<x<1), or a material consisting principally thereof and doped with hydrogen or halogen as a dangling bond neutralizer; wherein the non-single-crystal semiconductor has a first semiconductor region as a channel region a second and third semiconductor regions as a source and drain regions respectively connected with the opposing sides of the first semiconductor regions, respectively and having a P or N conductivity type and having a higher degree of conductivity than the first region; wherein the third, first and second regions are laterally arranged side by side in this order on the substrate; wherein the insulating layer is disposed on at least the first semiconductor region as a gate insulating layer; wherein the conductive layer is disposed on at least the first semiconductor region through the insulating layer as a gate electrode; and wherein the first semiconductor region is formed primarily of a first semi-amorphous semiconductor, and wherein the second and third semiconductor regions are formed primarily of a second semi-amorphous semiconductor containing more microcrystalline semiconductor than the first semi-amorphous semiconductor.