Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
198 words
A method for making a high performance NPN bipolar transistor functioning in a current switch logic circuit comprising: forming a bipolar transistor within an isolated region of a monocrystalline silicon body wherein said transistor includes an N+ subcollector, a N collector reach-through which connects said subcollector to a major surface of said body, a P base region above said subcollector and adjacent to said reach-through, an N+ emitter region within said base region and extending from said major surface, and wherein said base region includes an intrinsic base region located below said emitter region and an extrinsic base region located extending from said major surface and adjacent to said emitter region; forming a mask above said major surface which has openings therein only in the areas above major portions of said extrinsic base regions; forming a P+ region in said extrinsic base region by ion implanting with a P type dopant and to a depth of less than the depth of said N emitter region; annealing the structure to activate the P type dopant in the P+ region; and making electrical ohmic contact to the elements of said transistor and connecting them in said current switch logic circuit.
Claim 2
Independent Claim
198 words
A method for making a high performance NPN bipolar transistor functioning in a current switch logic circuit comprising: forming a bipolar transistor within an isolated region of a monocrystalline silicon body wherein said transistor includes an N+ subcollector, a N collector reach-through which connects said subcollector to a major surface of said body, a P base region above said subcollector and adjacent to said reach-through, an N+ emitter region within said base region and extending from said major surface, and wherein said base region includes an intrinsic base region located below said emitter region and an extrinsic base region located extending from said major surface and adjacent to said emitter region; forming a mask above said major surface which has openings therein only in the areas above major portions of said extrinsic base regions; forming a P+ region in said extrinsic base region by ion implanting with a P type dopant and to a depth of less than the depth of said N emitter region; annealing the structure to activate the P type dopant in the P+ region; and making electrical ohmic contact to the elements of said transistor and connecting them in said current switch logic circuit.
Claim 3
Dependent Claim
28 words
The method of claim 1 wherein the said intrinsic base region has a dopant concentration of between about 5×10 18 to 5×10 19 boron ions/cc. at the surface.
Claim 4
Dependent Claim
17 words
The method of claim 1 wherein said mask is composed of an exposed and developed resist material.
Claim 5
Dependent Claim
34 words
The method of claim 1 wherein said emitter-intrinsic base junction is between about 400 to 500 nanometers from said major surface and said extrinsic base-collector junction depth is between about 650 to 750 nanometers.
Claim 6
Dependent Claim
24 words
The method of claim 1 wherein said P+ extrinsic base is an annulus shaped region which surrounds the side edge of said emitter region.
Claim 7
Dependent Claim
28 words
The method of claim 2 wherein said ion implanting is followed with an annealing at a temperature of between about 850° to 950° C. for a suitable time.
Claim 8
Dependent Claim
35 words
The method of claim 6 wherein said P+ region has a dopant concentration of between about 1×10 20 to 1×10 19 boron ions/cc. at the surface and sheet resistivity of less than about 100 ohms/square.
Claim 9
Dependent Claim
17 words
The method of claim 7 wherein the said sheet resistivity is between about 35 to 60 ohms/square.
Claim 10
Dependent Claim
27 words
The method of claim 5 wherein the spacing of edge of said P+ base adjacent to the said emitter edge is between about 0.6 to 1.1 micrometers.
Claim 11
Dependent Claim
25 words
The method of claim 9 wherein the distance between the emitter-intrinsic base junction and intrinsic base collector junction is between about 200 to 300 nanometers.
Claim 12
Dependent Claim
22 words
The method of claim 10 wherein said sheet resistivity of said P+ extrinsic base region is between about 35 to 60 ohms/square.
Claim 13
Dependent Claim
18 words
The method of claim 11 wherein said electrical ohmic contact to said elements is a metal silicide contact.