Vertical MESFET with air spaced gate electrode

Claim 1

A semiconductor field effect transistor device comprising: a semi-insulating substrate layer; a first common conductive layer of an n + conductivity type semiconductor material having a relatively large number of charged carriers on said semi-insulating layer; a first narrow post extending upright from said first conductive layer, said narrow post including an intermediate layer of n conductivity type material having a relatively small number of charged carriers on said layer and a second conductive layer of said n + conductivity type having a relatively large number of charged carriers on said intermediate layer; a first source electrode on said second conductive layer, including a metal heat sink and ground layer on said source electrode; a first pair of gate electrodes disposed respectively on and extending along opposite sides of said narrow post intermediate layer; a pair of drain electrodes extending from and along the upper surface of said first conductive layer, each drain electrode being positioned adjacent a respective side of said post and being displaced laterally from said post and spaced from respective gate electrodes and from said source electrode; first means at one end of said device connecting said drain electrodes together; a second means at the other end connecting said gate electrodes together and to said substrate layer; a second narrow post spaced along said first conductive layer from said first post, said second post including respective intermediate and second conductive layers, a second source electrode disposed on said second narrow post second conductive layer, said source electrodes being connected to said metal heat sink and ground layer, a second pair of gate electrodes disposed on opposite sides of said second narrow post, a third drain electrode extending from said first conductive layer, a first drain electrode of said pair being positioned between and spaced from said first and second narrow posts, said second and third drain electrodes being positioned adjacent and displaced laterally outward from respective sides of said posts, said posts and electrodes forming a cell of two vertical field effect transistors; said first means including a metal drain pad at one end of said cell on said first conductive layer having connections to said three drain electrodes spaced from said source electrodes, said second means including a metal gate pad at the other end of said cell on said substrate layer having connections to said gate electrodes; and an undercut through said first conductive layer at said other end providing a space between said gate electrode connections and said first conductive layer, said gate electrode connections providing a connecting metal bridge between said gate pad and gate electrodes over said space without contacting said first conductive layer.