Electrical isolation of circuit components of integrated circuits

Claim 1

A method of fabricating an integrated semiconductor network comprising the steps of: a. forming a first insulating layer upon one major face of a low resistivity semiconductor wafer; b. depositing a body of crystalline semiconductor material upon said One major face adjacent to said first insulating layer; c. forming a layer of high resistivity semiconductor material upon the other major face of said wafer; d. forming individual circuit components within said layer of high resistivity semiconductor material, said circuit components being covered by a second layer of insulating material on the said high resistivity layer; e. forming openings in said second insulating layer to uncover selected areas of selected ones of said circuit components, f. forming an electrically conductive pattern of conductor strips on and adherent to said second insulating layer, said conductor strips interconnecting said selected ones of the circuit components through said openings in said second insulating layer; and g. selectively etching predetermined areas of said second insulating layer respectively surrounding said circuit components and selectively etching areas of said high resistivity semiconductor material and of said low resistivity semiconductor wafer, underlying said predetermined areas of said second insulating layer through to the first insulating area without etching portions of said pattern of conductor strips over said predetermined areas of said second insulating area, thereby forming open mouth spaces separating semiconductor islands attached to said first insulating layer and containing said circuit components, said open mouth spaces being bridged by conductor strips of said pattern of conductor strips.

Claim 2

A method of fabricating an integrated semiconductor network comprising the steps of: a. forming a first insulating layer upon one major face of a low resistivity semiconductor wafer; b. depositing a body of crystalline semiconductor material upon said One major face adjacent to said first insulating layer; c. forming a layer of high resistivity semiconductor material upon the other major face of said wafer; d. forming individual circuit components within said layer of high resistivity semiconductor material, said circuit components being covered by a second layer of insulating material on the said high resistivity layer; e. forming openings in said second insulating layer to uncover selected areas of selected ones of said circuit components, f. forming an electrically conductive pattern of conductor strips on and adherent to said second insulating layer, said conductor strips interconnecting said selected ones of the circuit components through said openings in said second insulating layer; and g. selectively etching predetermined areas of said second insulating layer respectively surrounding said circuit components and selectively etching areas of said high resistivity semiconductor material and of said low resistivity semiconductor wafer, underlying said predetermined areas of said second insulating layer through to the first insulating area without etching portions of said pattern of conductor strips over said predetermined areas of said second insulating area, thereby forming open mouth spaces separating semiconductor islands attached to said first insulating layer and containing said circuit components, said open mouth spaces being bridged by conductor strips of said pattern of conductor strips.

Claim 4

A method of fabricating an integrated circuit of the type having a plurality of circuit components selectively interconnected with at least two of the circuit components electrically isolated from each other by a space selectively located therebetween, comprising the steps of: a. forming a first insulating layer upon one surface of a semiconductor body; b. forming a support on said first insulating layer; c. forming individual circuit components on the opposite surface of said semiconductor body by depositing a semiconductor layer of higher resistivity than said body on said opposite surface of said body and introducing impurities into said semiconductor layer, said circuit components being covered by a second layer of insulating material; d. forming openings in said second insulating layer to uncover selected areas of selected ones of said circuit components; e. forming an electrically conductive pattern of metal strips on and adherent to said second insulating layer, said metal strips interconnecting said selected ones of the circuit components through said openings in the second insulating layer; and f. selectively removing portions of said second insulating layer between at least two of said circuit components interconnected by said metal strips and selectively removing portions of said semiconductor layer and said semiconductor body underlying said removed portions of said second insulating layer, thereby forming an elongated open mouth channel providing electrical isolation between said at least two circuit components, said channel being bridged by at least one metal strip interconnecting said at least two circuit components.

Claim 5

A method of fabricating an integrated circuit of the type having a plurality of circuit components selectively interconnected with at least two of the circuit components electrically isolated from each other by a space selectively located therebetween, comprising the steps of: a. forming a first insulating layer upon one surface of a semiconductor body; b. forming a support on said first insulating layer; c. forming individual circuit components on the opposite surface of said semiconductor body by depositing a semiconductor layer of higher resistivity than said body on said opposite surface of said body and introducing impurities into said semiconductor layer, said circuit components being covered by a second layer of insulating material; d. forming openings in said second insulating layer to uncover selected areas of selected ones of said circuit components; e. forming an electrically conductive pattern of metal strips on and adherent to said second insulating layer, said metal strips interconnecting said selected ones of the circuit components through said openings in the second insulating layer; and f. selectively removing portions of said second insulating layer between at least two of said circuit components interconnected by said metal strips and selectively removing portions of said semiconductor layer and said semiconductor body underlying said removed portions of said second insulating layer, thereby forming an elongated open mouth channel providing electrical isolation between said at least two circuit components, said channel being bridged by at least one metal strip interconnecting said at least two circuit components.

Claim 6

A method of fabricating a integrated circuit of the type having a plurality of circuit components selectively interconnected with at least two of the circuit components electrically isolated from each other by a space selectively located therebetween, comprising the steps of: a. forming a first insulating layer upon one major surface of a semiconductor body; b. forming a support on said insulating Layer; c. forming a plurality of individual components on another major surface of said semiconductor body by depositing layers of semiconductor material thereover and introducing impurities therein, said circuit components being covered by a second insulating layer and at least two of said circuit components being electrically connected by portions of semiconductor material located therebetween; d. forming an electrically conductive pattern of conductor strips on and adherent to said second insulating layer, said conductor strips interconnecting said circuit components; and e. selectively removing a portion of said second insulating layer between said at least two circuit components and selectively removing portions of said deposited layers of semiconductor material and of said semiconductor body between said at least two circuit components which electrically connect said circuit components, thereby forming an elongated, open mouth space between said at least two circuit components to provide electrical isolation therebetween, said elongated open mouth space being bridged by at least one metal strip interconnecting said at least two circuit components.

Claim 7

A method of fabricating a integrated circuit of the type having a plurality of circuit components selectively interconnected with at least two of the circuit components electrically isolated from each other by a space selectively located therebetween, comprising the steps of: a. forming a first insulating layer upon one major surface of a semiconductor body; b. forming a support on said insulating Layer; c. forming a plurality of individual components on another major surface of said semiconductor body by depositing layers of semiconductor material thereover and introducing impurities therein, said circuit components being covered by a second insulating layer and at least two of said circuit components being electrically connected by portions of semiconductor material located therebetween; d. forming an electrically conductive pattern of conductor strips on and adherent to said second insulating layer, said conductor strips interconnecting said circuit components; and e. selectively removing a portion of said second insulating layer between said at least two circuit components and selectively removing portions of said deposited layers of semiconductor material and of said semiconductor body between said at least two circuit components which electrically connect said circuit components, thereby forming an elongated, open mouth space between said at least two circuit components to provide electrical isolation therebetween, said elongated open mouth space being bridged by at least one metal strip interconnecting said at least two circuit components.

Claim 8

A method of fabricating an integrated circuit of the type having a plurality of circuit components selectively interconnected with at least two of the circuit components electrically isolated from each other by a channel or moat selectively located therebetween, comprising the steps of: a. forming a first insulating layer of a semiconductor compound upon one major surface of a semiconductor body; b. forming a support on said first insulating layer; c. forming a plurality of individual circuit components on another major surface of said semiconductor body by depositing semiconductor material thereover and introducing impurities therein, said circuit components being covered by a second layer of insulating material comprising a semiconductor compound and with at least two of said circuit components being electrically connected by portions of said semiconductor body located therebetween; d. forming an electrically conductive layer over and adherent to said second insulating layer; e. selectively removing areas of said conductive layer to form an electrically conductive pattern of conductor strips on and adherent to said second insulating layer, said conductor strips selectively interconnecting said circuit components; and f. selectively etching portions of said second insulating layer around and under conductor strips interconnecting said at least two circuit components and selectively etching portions of said deposited semiconductor material and of said semiconductor body underlying said removed portions of said second insulating layer to form an elongated open mouth channel or moat extending to said first insulating layer and thereby electrically isolating said at least two circuit elements from one another, said at least two circuit components being interconnected by conductor strips bridging said channel or moat.

Claim 9

A method of fabricating an integrated circuit of the type having a plurality of circuit components selectively interconnected with at least two of the circuit components electrically isolated from each other by a channel or moat selectively located therebetween, comprising the steps of: a. forming a first insulating layer of a semiconductor compound upon one major surface of a semiconductor body; b. forming a support on said first insulating layer; c. forming a plurality of individual circuit components on another major surface of said semiconductor body by depositing semiconductor material thereover and introducing impurities therein, said circuit components being covered by a second layer of insulating material comprising a semiconductor compound and with at least two of said circuit components being electrically connected by portions of said semiconductor body located therebetween; d. forming an electrically conductive layer over and adherent to said second insulating layer; e. selectively removing areas of said conductive layer to form an electrically conductive pattern of conductor strips on and adherent to said second insulating layer, said conductor strips selectively interconnecting said circuit components; and f. selectively etching portions of said second insulating layer around and under conductor strips interconnecting said at least two circuit components and selectively etching portions of said deposited semiconductor material and of said semiconductor body underlying said removed portions of said second insulating layer to form an elongated open mouth channel or moat extending to said first insulating layer and thereby electrically isolating said at least two circuit elements from one another, said at least two circuit components being interconnected by conductor strips bridging said channel or moat.