US4129879A
Expired / Lapsed
US
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Vertical field effect transistor
Assignee: General Electric Co
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Filing: 1978-05-22
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Granted: 1978-12-12
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Expires: 1998-05-22
Abstract
Abstract An interdigitated field effect transistor for high power, high frequency applications has a vertical configuration with current flow essentially normal to the surface, as compared to planar devices in which current flow is parallel to the surface. Each channel region is of the same conductivity type as the source and drain regions and is in a mesa structure surrounded by the gate metallization such that the gate metal forms an electronically blocking contact to the channel semiconductor. The device geometry has a natural strip line configuration.
Inventors
- 👤 Wirojana Tantraporn
- 👤 Se P. Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/63; H10D30/80; H10D30/87; H10D30/871
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
157 words
A field effect transistor comprising a first outer heavily doped semiconductor layer upstanding from which is a mesa structure comprising an inner moderately doped semiconductor layer and a second outer heavily doped semiconductor layer, all of said semiconductor layers being of the same conductivity type and one of said outer layers being the source region while the other is the drain region and said inner layer is the channel region, contact metallizations on the external opposing surfaces of the outer semiconductor layers, an insulating layer attached to the inner surface of said first outer layer surrounding said mesa structure, and gate metallization on said insulating layer and surrounding said mesa structure so as to be adjacent to the side edges of said inner semiconductor layer and define an electronically blocking contact to the channel region, said channel region consisting of the entire inner semiconductor layer and extending from edge to edge of the mesa structure without interruption.
Claim 2
Dependent Claim
157 words
A field effect transistor comprising a first outer heavily doped semiconductor layer upstanding from which is a mesa structure comprising an inner moderately doped semiconductor layer and a second outer heavily doped semiconductor layer, all of said semiconductor layers being of the same conductivity type and one of said outer layers being the source region while the other is the drain region and said inner layer is the channel region, contact metallizations on the external opposing surfaces of the outer semiconductor layers, an insulating layer attached to the inner surface of said first outer layer surrounding said mesa structure, and gate metallization on said insulating layer and surrounding said mesa structure so as to be adjacent to the side edges of said inner semiconductor layer and define an electronically blocking contact to the channel region, said channel region consisting of the entire inner semiconductor layer and extending from edge to edge of the mesa structure without interruption.
Claim 3
Dependent Claim
42 words
A field effect transistor according to claim 1 wherein all of said semiconductor layers are made of n-type gallium arsenide and wherein the electronically blocking contact of said gate metallization to the channel region in said mesa structure is a Schottky junction.
Claim 4
Dependent Claim
194 words
An interdigitated field effect transistor comprising a first outer heavily doped semiconductor layer on which is formed a plurality of parallel elongated mesa structures each comprising an inner moderately doped semiconductor layer and a second outer heavily doped semiconductor layer, all of said semiconductor layers being of the same conductivity type and one of said outer semiconductor layers being the source region while the other is the drain region and said inner layer is the channel region, contact metallizations on the external surface of said first outer layer and on the external surface of the second outer layer in each mesa structure, and an interconnection metallization coupling together the contact metallizations on said mesa structures, an insulating layer attached to the inner surface of said first outer layer surrounding said mesa structures, and gate metallization on said insulating layer and surrounding said mesa structures so as to be adjacent to the side edges of the inner semiconductor layers in said mesa structures and define electronically blocking contacts to the channel regions, said channel regions each consisting of the entire inner semiconductor layer and extending from edge to edge of the mesa structure without interruption.
Claim 5
Dependent Claim
194 words
An interdigitated field effect transistor comprising a first outer heavily doped semiconductor layer on which is formed a plurality of parallel elongated mesa structures each comprising an inner moderately doped semiconductor layer and a second outer heavily doped semiconductor layer, all of said semiconductor layers being of the same conductivity type and one of said outer semiconductor layers being the source region while the other is the drain region and said inner layer is the channel region, contact metallizations on the external surface of said first outer layer and on the external surface of the second outer layer in each mesa structure, and an interconnection metallization coupling together the contact metallizations on said mesa structures, an insulating layer attached to the inner surface of said first outer layer surrounding said mesa structures, and gate metallization on said insulating layer and surrounding said mesa structures so as to be adjacent to the side edges of the inner semiconductor layers in said mesa structures and define electronically blocking contacts to the channel regions, said channel regions each consisting of the entire inner semiconductor layer and extending from edge to edge of the mesa structure without interruption.
Claim 6
Dependent Claim
41 words
A field effect transistor according to claim 3 wherein all of said semiconductor layers are made of n-type gallium arsenide and wherein the electronically blocking contacts of said gate metallization to the channel regions in said mesa structures are Schottky junctions.
Claim 7
Dependent Claim
65 words
A field effect transistor according to claim 4 wherein said insulating layer is continuous and extends into a depression in said first outer semiconductor layer and wherein said gate metallization is a continuous layer of uniform thickness in approximately the same plane as said inner semiconductor layer with the thickness of said gate metallization being no greater than the thickness of said inner semiconductor layer.
Claim 8
Dependent Claim
33 words
A field effect transistor according to claim 4 or claim 5 wherein the width of each elongated channel region from edge to edge of the mesa structure is no greater than one micron.
References Cited (Backward Citations)
US3761785A
Cited
US3851379A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-12-11 | 1982-06-12 | 1982-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-12-11 | 1986-06-12 | 1986-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-12-11 | 1990-06-12 | 1990-12-12 | $7700.00 | Window Closed / Lapsed |