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Patent US4567646A successfully refreshed from Google Patents.
US4567646A
Expired / Lapsed
US
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Method for fabricating a dielectric isolated integrated circuit device
Assignee: Fujitsu Ltd
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Filing: 1984-11-30
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Granted: 1986-02-04
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Expires: 2004-11-30
Abstract
Abstract A method for fabricating a wafer for a dielectric isolation (DI) integrated circuit device is provided, wherein the substrate of the wafer, comprises portions of polycrystalline silicon positioned beneath regions for electrical elements, namely, "islands", and portions of single crystal silicon are positioned in other areas of the wafer such as scribing regions, peripheral regions and contact regions. The single crystal portions of the substrate are grown during its fabricating steps by exposing surfaces of an original substrate of single crystal silicon, before the deposition of silicon onto the original substrate, by removing a dielectric isolation layer over the predetermined regions to be exposed. The single crystal silicon portions of the wafer provide various advantages for subsequent mechanical processing of the wafer such as shaping and rounding of the peripheral region and the scribing of the wafer into dice.
Inventors
- 👤 Tamotsu Ishikawa
- 👤 Hirokazu Tanaka
- 👤 Akira Tabata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:10
CPC Classifications
H; H10; H10W; H10W10/00; H10D; H10D99/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/026; Y10S148/085; Y10S148/122; Y10S438/00; Y10S438/969; Y10S438/977
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
148 words
A method for fabricating a dielectric isolation (DI) integrated circuit device comprising the steps of: (a) preparing a one conductivity type doped single crystal siilcon original substrate having a peripheral region and an interior region; (b) forming isolation moates on a surface of said original substrate; (c) forming a dielectric isolation layer over a first portion of the interior region of the surface of said original substrate, said first portion of the surface being the areas wherein electrical circuit elements are to be formed; (d) exposing said peripheral region of the surface of said original substrate, not including said first portion of the surface; and (e) growing a silicon layer over the entire portion of the surface of said original substrate, wherein said grown silicon layer comprises a single crystal silicon over said peripheral region of said surface and a polysilicon over said first portion of said surface.
Claim 2
Independent Claim
148 words
A method for fabricating a dielectric isolation (DI) integrated circuit device comprising the steps of: (a) preparing a one conductivity type doped single crystal siilcon original substrate having a peripheral region and an interior region; (b) forming isolation moates on a surface of said original substrate; (c) forming a dielectric isolation layer over a first portion of the interior region of the surface of said original substrate, said first portion of the surface being the areas wherein electrical circuit elements are to be formed; (d) exposing said peripheral region of the surface of said original substrate, not including said first portion of the surface; and (e) growing a silicon layer over the entire portion of the surface of said original substrate, wherein said grown silicon layer comprises a single crystal silicon over said peripheral region of said surface and a polysilicon over said first portion of said surface.
Claim 3
Dependent Claim
27 words
A method for fabricating a dielectric isolation (DI) integrated circuit device of claim 1, wherein said dielectric isolation layer is a silicon dioxide (SiO 2 ) layer.
Claim 4
Dependent Claim
87 words
A method of fabricating a dielectric isolation (DI) integrated circuit device as set forth in claim 1, wherein preparing said original substrate comprises the steps of : (a) forming a silicon dioxide layer on the surface of said original substrate, said silicon dioxide layer having windows at predetermined locations therein; (b) forming a silicon nitride (Si 3 N 4 ) layer on predetermined portions of said silicon dioxide layer; and (c) wherein said moats are formed in the areas beneath the windows in said silicon dioxide layer.
Claim 5
Dependent Claim
40 words
A method of fabricating a dielectric isolation (DI) integrated circuit device as set forth in claim 3, wherein exposing said peripheral region of the surface comprises removing said predetermined portions of said silicon dioxide layer and said silicon nitride layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-03 | 1989-08-05 | 1990-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-03 | 1993-08-05 | 1994-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-03 | 1997-08-05 | 1998-02-04 | $7700.00 | Window Closed / Lapsed |