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Patent US4567578A successfully refreshed from Google Patents.
US4567578A
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Cache memory flush scheme
Assignee: Intersil Corp
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Filing: 1982-09-08
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Granted: 1986-01-28
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Expires: 2002-09-08
Abstract
Abstract A method of setting a memory array to a common logic value by activating all the line switches by the precharge device for the duration of a word signal and simultaneously applying the common logic value directly to all the bit lines.
Inventors
- 👤 Paul Cohen
- 👤 William R Young
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:18
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/20; G11C8/00; G11C8/10; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0891
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
123 words
In a memory having a memory array, a word decoder and a bit decoder, the improvement comprising: said word decoder including for each word line a word line switch means for connecting a word line signal to said word line when activated by said word decoder in response to a word address and a word precharge means for activating said word line switch prior to word decoding; and write means activating said word precharge means in response to an all write signal for connecting a word line signal to said word line and for writing a specific logic value in all the memory locations in said memory array simultaneously in response to said all write signal without addressing said word and bit decoders.
Claim 2
Dependent Claim
123 words
In a memory having a memory array, a word decoder and a bit decoder, the improvement comprising: said word decoder including for each word line a word line switch means for connecting a word line signal to said word line when activated by said word decoder in response to a word address and a word precharge means for activating said word line switch prior to word decoding; and write means activating said word precharge means in response to an all write signal for connecting a word line signal to said word line and for writing a specific logic value in all the memory locations in said memory array simultaneously in response to said all write signal without addressing said word and bit decoders.
Claim 3
Dependent Claim
101 words
In a memory having a memory array, a word decoder and a bit decoder, the improvement comprising: word means connected to all word lines of said memory array for activating all the word lines of said memory array in response to an all write signal during a low chip enable period without addressing said word decoder, and bit means connected to all the bit lines of said memory array for simultaneously writing a specific logic value into all the memory locations in said memory array via said bit lines in response to said all write signal without addressing said bit decoder.
Claim 4
Dependent Claim
101 words
In a memory having a memory array, a word decoder and a bit decoder, the improvement comprising: word means connected to all word lines of said memory array for activating all the word lines of said memory array in response to an all write signal during a low chip enable period without addressing said word decoder, and bit means connected to all the bit lines of said memory array for simultaneously writing a specific logic value into all the memory locations in said memory array via said bit lines in response to said all write signal without addressing said bit decoder.
Claim 5
Dependent Claim
47 words
The memory according to claim 2, including bit precharge means for precharging said bit lines, and wherein said word decoder includes for each word line disable means connected to each of said word lines for disabling all of said word lines during operation of said precharge means.
Claim 6
Independent Claim
111 words
A method of writing a common logic value in a memory, said memory including a memory array, a word decoder for each word line in said array with a line switch for transmitting a word signal when activated by said word decoder in response to a word address, precharge means for activating said line switch in a precharge cycle, and a bit line decoder for each bit line comprising the steps of: activating said precharge means to activate all said word line switches; transmitting a word signal through all of said word line switches held activated by said precharge means; and applying a common logic signal to all said bit lines.
Claim 7
Independent Claim
111 words
A method of writing a common logic value in a memory, said memory including a memory array, a word decoder for each word line in said array with a line switch for transmitting a word signal when activated by said word decoder in response to a word address, precharge means for activating said line switch in a precharge cycle, and a bit line decoder for each bit line comprising the steps of: activating said precharge means to activate all said word line switches; transmitting a word signal through all of said word line switches held activated by said precharge means; and applying a common logic signal to all said bit lines.
Claim 8
Dependent Claim
36 words
The method according to claim 4, wherein said step of applying a common logic signal to all said bit lines include providing said common logic signal directly to said bit lines without said bit line decoder.
Claim 9
Dependent Claim
148 words
In a memory having a memory array, a word decoder and a bit decoder, the improvement comprising: said word decoder includes for each word line a word line switch means for connecting a word line signal to said word lines when activated by said word decoder in response to a word address; word means connected to all word line switch means of said memory array for activating all the word line switch means of said memory array in response to an all write signal without addressing and irrespective of said word decoder to connect said word line signal to all said word lines; and bit means connected to all the bit lines of said memory array for simultaneously writing a specific logic value into all the memory locations in said memory array via said bit lines in response to said all write signal without addressing said bit decoder.
Claim 10
Dependent Claim
148 words
In a memory having a memory array, a word decoder and a bit decoder, the improvement comprising: said word decoder includes for each word line a word line switch means for connecting a word line signal to said word lines when activated by said word decoder in response to a word address; word means connected to all word line switch means of said memory array for activating all the word line switch means of said memory array in response to an all write signal without addressing and irrespective of said word decoder to connect said word line signal to all said word lines; and bit means connected to all the bit lines of said memory array for simultaneously writing a specific logic value into all the memory locations in said memory array via said bit lines in response to said all write signal without addressing said bit decoder.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-27 | 1989-07-29 | 1990-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-27 | 1993-07-29 | 1994-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-27 | 1997-07-29 | 1998-01-28 | $7700.00 | Window Closed / Lapsed |