Preset circuit for information storage devices

Claim 2

An electronic circuit for erasing an information bit stored in a bistable semiconductor cell and entering a predetermined new information bit into said cell, thereby to set said cell in a predetermined one of two possible states, wherein said cell includes two transistors arranged in a bistable configuration for information bit storage and wherein the state of said cell is sustainable by current provided from at least one current source through a standard current-source conductor to said cell, said electronic circuit comprising: an additional current-conducting region formed as part of a selected transistor of said two transistors, said predetermined new information bit being defined by the state of said cell when said selected transistor is conducting; an additional conductor coupled to said selected transistor through said additional current-conducting region; and a current switch coupled to said at least one current source and coupled to said conductors for switching current from said standard current-source conductor to said additional conductor at a signal supplied to said current switch from an external signal source, whereby said information bit is erased and said predetermined new information bit is entered in said cell.

Claim 3

An electronic circuit for erasing an information bit stored in a bistable semiconductor cell and entering a predetermined new information bit into said cell, thereby to set said cell in a predetermined one of two possible states, wherein said cell includes two transistors arranged in a bistable configuration for information bit storage, said electronic circuit comprising: an additional current-conducting region formed as part of a selected transistor of said two transistors, said predetermined new information bit being defined by the state of said cell when said selected transistor is conducting; a standard current-source conductor coupled to said two transistors for conducting current to said cell to sustain the state of said cell; an additional conductor coupled to said selected transistor through said additional current-conducting region; at least one current source for providing current either to said cell through said standard current-source conductor or to said selected transistor through said additional conductor; and a current switch coupled to said at least one current source and coupled to said conductors for switching current from said standard current-source conductor to said additional conductor at a signal supplied to said current switch from an external signal source, whereby said information bit is erased and said predetermined new information bit is entered in said cell.

Claim 4

An electronic circuit for erasing an information bit stored in a bistable semiconductor cell and entering a predetermined new information bit into said cell, thereby to set said cell in a predetermined one of two possible states, wherein said cell includes two transistors arranged in a bistable configuration for information bit storage, said electronic circuit comprising: an additional current-conducting region formed as part of a selected transistor of said two transistors, said predetermined new information bit being defined by the state of said cell when said selected transistor is conducting; a standard current-source conductor coupled to said two transistors for conducting current to said cell to sustain the state of said cell; an additional conductor coupled to said selected transistor through said additional current-conducting region; at least one current source for providing current either to said cell through said standard current-source conductor or to said selected transistor through said additional conductor; and a current switch coupled to said at least one current source and coupled to said conductors for switching current from said standard current-source conductor to said additional conductor at a signal supplied to said current switch from an external signal source, whereby said information bit is erased and said predetermined new information bit is entered in said cell.

Claim 5

An electronic circuit for information bit storage having a capability for erasing an information bit stored in said electronic circuit and entering a predetermined new information bit into said electronic circuit, said electronic circuit comprising: a bistable semiconductor cell having two transistors arranged in a bistable configuration, thereby to permit said cell to exist in one of two possible states; an additional current-conducting region formed as part of a selected transistor of said two transistors, said predetermined new information bit being defined by the state of said cell when said selected transistor is conducting; a standard current-source conductor coupled to said two transistors for conducting current to said cell to sustain the state of said cell; an additional conductor coupled to said selected transistor through said additional current-conducting region; and a current switch coupled to said conductors for switching current from said standard current-source conductor to said additional conductor at a signal supplied to said current switch from an external signal source, whereby said information bit is erased and said predetermined new information bit is entered in said cell.

Claim 6

An electronic circuit for information bit storage having a capability for erasing an information bit stored in said electronic circuit and entering a predetermined new information bit into said electronic circuit, said electronic circuit comprising: a bistable semiconductor cell having two transistors arranged in a bistable configuration, thereby to permit said cell to exist in one of two possible states; an additional current-conducting region formed as part of a selected transistor of said two transistors, said predetermined new information bit being defined by the state of said cell when said selected transistor is conducting; a standard current-source conductor coupled to said two transistors for conducting current to said cell to sustain the state of said cell; an additional conductor coupled to said selected transistor through said additional current-conducting region; and a current switch coupled to said conductors for switching current from said standard current-source conductor to said additional conductor at a signal supplied to said current switch from an external signal source, whereby said information bit is erased and said predetermined new information bit is entered in said cell.

Claim 7

An electronic circuit according to claim 3 and further including at least one current source coupled to said current switch for providing current either to said cell through said standard current-source conductor to to said selected transistor through said additional conductor.

Claim 8

An electronic circuit according to claim 1 or 4 wherein said two transistors are bipolar transistors and said additional current-conducting region is an emitter region.

Claim 9

An electronic circuit according to claim 5 wherein said current switch includes: a third bipolar transistor, the collector of said third transistor being connected to said additional conductor and the base of said third transistor being coupled to said external signal source; a fourth bipolar transistor, the collector of said fourth transistor being connected to said standard current-source conductor, the base of said fourth transistor being connected to a first current source of said at least one current source, and the emitter of said fourth transistor being connected to the emitter of said third transistor; and a resistor connected between a second current source of said at least one current source and the interconnected emitters of said third and fourth transistors.

Claim 10

An electronic circuit according to claim 5 wherein the bistable configuration for said two transistors of said cell is formed by: coupling the collector of said first transistor to the base of said second transistor; coupling the collector of said second transistor to the base of said first transistor; and coupling a first emitter of said first transistor to a first emitter of said second transistor.

Claim 11

An electronic circuit according to claim 5 wherein said two bipolar transistors are NPN transistors.

Claim 12

An electronic circuit according to claim 5 wherein said two bipolar transistors are PNP transistors.

Claim 13

An electronic circuit according to claim 6 wherein said third and fourth bipolar transistors are NPN transistors.

Claim 14

An electronic circuit according to claim 6 wherein said third and fourth bipolar transistors are PNP transistors.

Claim 15

An electronic circuit for information storage having a capability for simultaneously erasing the information contained in said electronic circuit and entering a predetermined new pattern of information into said electronic circuit, said electronic circuit comprising: a plurality of bistable semiconductor cells arranged in an array of M word rows and N bit columns, where M and N are positive integers and N is greater than one, each of said cells having two transistors arranged in a bistable configuration for information bit storage, thereby to permit each cell to exist in one of two possible states, and each cell having an additional current conducting region formed as part of a selected transistor of said two transistors in said cell, the predetermined new information bit in said cell being defined by the state of said cell when said selected transistor is conducting; M standard current-source word-line conductors corresponding on a one-to-one basis to said M rows, each standard current-source word-line conductor being coupled to the cells in the corresponding row for conducting current to the cells in said corresponding row to sustain the states of said cells in said corresponding row; M additional word-line conductors corresponding on a one-to-one basis to said M rows, each additional word-line conductor being coupled to said selected transistors in the cells of the corresponding row through the additional current-conducting regions in the cells of said corresponding row; and M current switches corresponding on a one-to-one basis to said M rows, each current switch being coupled to the standard current-source word-line conductor for the corresponding row and being coupled to the additional word-line conductor for said corresponding row for switching current from said standard current-source word-line conductor for said corresponding row to said additional word-line conductor for said corresponding row at a signal supplied to said M current switches from an external signal source, whereby said information is erased from said cells and said predetermined new pattern of information is entered into said cells.

Claim 16

An electronic circuit for information storage having a capability for simultaneously erasing the information contained in said electronic circuit and entering a predetermined new pattern of information into said electronic circuit, said electronic circuit comprising: a plurality of bistable semiconductor cells arranged in an array of M word rows and N bit columns, where M and N are positive integers and N is greater than one, each of said cells having two transistors arranged in a bistable configuration for information bit storage, thereby to permit each cell to exist in one of two possible states, and each cell having an additional current conducting region formed as part of a selected transistor of said two transistors in said cell, the predetermined new information bit in said cell being defined by the state of said cell when said selected transistor is conducting; M standard current-source word-line conductors corresponding on a one-to-one basis to said M rows, each standard current-source word-line conductor being coupled to the cells in the corresponding row for conducting current to the cells in said corresponding row to sustain the states of said cells in said corresponding row; M additional word-line conductors corresponding on a one-to-one basis to said M rows, each additional word-line conductor being coupled to said selected transistors in the cells of the corresponding row through the additional current-conducting regions in the cells of said corresponding row; and M current switches corresponding on a one-to-one basis to said M rows, each current switch being coupled to the standard current-source word-line conductor for the corresponding row and being coupled to the additional word-line conductor for said corresponding row for switching current from said standard current-source word-line conductor for said corresponding row to said additional word-line conductor for said corresponding row at a signal supplied to said M current switches from an external signal source, whereby said information is erased from said cells and said predetermined new pattern of information is entered into said cells.

Claim 17

An electronic circuit according to claim 12 and further including at least one word-line current source coupled to said M current siwtches for providing current either to said cells through said M standard current-source word-line conductors or to said selected transistors through said M additional word-line conductors.

Claim 18

An electronic circuit for simultaneously erasing the information contained in an information storage device and entering a predetermined new pattern of information into said information storage device, wherein said information storage device includes: a plurality of bistable semiconductor cells arranged in an array of M word rows and N bit columns, where M and N are positive integers and N is greater than one, each of said cells having two transistors arranged in a bistable configuration for information bit storage, thereby to permit each cell to exist in one of two possible states, said two transistors being designated as a left-hand transistor and a right-hand transistor; M upper word-line conductors corresponding on a one-to-one basis to said M rows, each upper word-line conductor being coupled to the cells in the corresponding row; row-addressing means connected to said M upper word-line conductors for addressing at least one selected row; M standard current-source word-line conductors corresponding on a one-to-one basis to said M rows, each standard current-source word-line conductor being coupled to the cells in the corresponding row for conducting current to the cells in said corresponding row to sustain the states of said cells in said corresponding row; N left-hand bit-line conductors corresponding on a one-to-one basis to said N columns, each left-hand bit-line conductor being coupled to the left-hand transistors in the cells of the corresponding column; N right-hand bit-line conductors corresponding on a one-to-one basis to said N columns, each right-hand bit-line conductor being coupled to the right-hand transistors in the cells of the corresponding column; and column-addressing means connected to said 2N bit-line conductors for addressing at least one selected column; said electronic circuit comprising: a plurality of additional current-conducting regions corresponding on a one-to-one basis to said plurality of cells, each additional current-conducting region being formed as part of a selected transistor of said two transistors in each cell, the predetermined new information bit in each cell being defined by the state of said cell when said selected transistor in said cell is conducting; M additional word-line conductors corresponding on a one-to-one basis to said M rows, each additional word-line conductor being coupled to said selected transistors in the cells of the corresponding row through the additional current-conducting regions in the cells of said corresponding row; M current switches corresponding on a one-to-one basis to said M rows, each current switch being coupled to the standard current-source word-line conductor for the corresponding row and being coupled to the additional word-line conductor for said corresponding row for switching current from said standard current-source word-line conductor for said corresponding row to said additional word-line conductor for said corresponding row; and signal means coupled to at least one of said row-addressing means and said column-addressing means and coupled to said M current switches for providing a signal to said M current switches to cause each current switch to switch current from the standard current-source word-line conductor for the corresponding row to the additional word-line conductor for said corresponding row, whereby said present information is erased from said cells and said predetermined new pattern of information is entered into said cells.

Claim 19

An electronic circuit for simultaneously erasing the information contained in an information storage device and entering a predetermined new pattern of information into said information storage device, wherein said information storage device includes: a plurality of bistable semiconductor cells arranged in an array of M word rows and N bit columns, where M and N are positive integers and N is greater than one, each of said cells having two transistors arranged in a bistable configuration for information bit storage, thereby to permit each cell to exist in one of two possible states, said two transistors being designated as a left-hand transistor and a right-hand transistor; M upper word-line conductors corresponding on a one-to-one basis to said M rows, each upper word-line conductor being coupled to the cells in the corresponding row; row-addressing means connected to said M upper word-line conductors for addressing at least one selected row; M standard current-source word-line conductors corresponding on a one-to-one basis to said M rows, each standard current-source word-line conductor being coupled to the cells in the corresponding row for conducting current to the cells in said corresponding row to sustain the states of said cells in said corresponding row; N left-hand bit-line conductors corresponding on a one-to-one basis to said N columns, each left-hand bit-line conductor being coupled to the left-hand transistors in the cells of the corresponding column; N right-hand bit-line conductors corresponding on a one-to-one basis to said N columns, each right-hand bit-line conductor being coupled to the right-hand transistors in the cells of the corresponding column; and column-addressing means connected to said 2N bit-line conductors for addressing at least one selected column; said electronic circuit comprising: a plurality of additional current-conducting regions corresponding on a one-to-one basis to said plurality of cells, each additional current-conducting region being formed as part of a selected transistor of said two transistors in each cell, the predetermined new information bit in each cell being defined by the state of said cell when said selected transistor in said cell is conducting; M additional word-line conductors corresponding on a one-to-one basis to said M rows, each additional word-line conductor being coupled to said selected transistors in the cells of the corresponding row through the additional current-conducting regions in the cells of said corresponding row; M current switches corresponding on a one-to-one basis to said M rows, each current switch being coupled to the standard current-source word-line conductor for the corresponding row and being coupled to the additional word-line conductor for said corresponding row for switching current from said standard current-source word-line conductor for said corresponding row to said additional word-line conductor for said corresponding row; and signal means coupled to at least one of said row-addressing means and said column-addressing means and coupled to said M current switches for providing a signal to said M current switches to cause each current switch to switch current from the standard current-source word-line conductor for the corresponding row to the additional word-line conductor for said corresponding row, whereby said present information is erased from said cells and said predetermined new pattern of information is entered into said cells.

Claim 20

An electronic circuit for information storage having a capability for simultaneously erasing the present information contained in said electronic circuit and entering a predetermined new pattern of information into said electronic circuit, said electronic circuit comprising: a plurality of bistable semiconductor cells arranged in an array of M word rows and N bit columns, where M and N are positive integers and N is greater than one, each of said cells having two transistors arranged in a bistable configuration for information bit storage, thereby to permit each cell to exist in one of two possible states, said two transistors being designated as a left-hand transistor and a right-hand transistor, and each cell having an additional current conducting region formed as part of a selected transistor of said two transistors in said cell, the predetermined new information bit in said cell being defined by the state of said cell when said selected transistor is conducting; M upper word-line conductors corresponding on a one-to-one basis to said M rows, each upper word-line conductor being coupled to the cells in the corresponding row; row-addressing means connected to said M upper word-line conductors for addressing at least one selected row; M standard current-source word-line conductors corresponding on a one-to-one basis to said M rows, each standard current-source word-line conductor being coupled to the cells in the corresponding row for conducting current to the cells in said corresponding row to sustain the states of said cells in said corresponding row; N left-hand bit-line conductors corresponding on a one-to-one basis to said N columns, each left-hand bit-line conductor being coupled to the left-hand transistors in the cells of the corresponding column; N right-hand bit-line conductors corresponding to a one-to-one basis to said N columns, each right-hand bit-line conductor being coupled to the right-hand transistors in the cells of the corresponding column; column-addressing means connected to said 2N bit-line conductors for addressing at least one selected column; M additional word-line conductors corresponding on a one-to-one basis to said M rows, each additional word-line conductor being coupled to the selected transistors in the cells of the corresponding row through the additional current-conducting regions in the cells of said corresponding row; M current switches corresponding on a one-to-one basis to said M rows, each current switch being coupled to the standard current-source word-line conductor for the corresponding row and being coupled to the additional word-line conductor for said corresponding row for switching current from said standard current-source word-line conductor for said corresponding row to said additional word-line conductor for said corresponding row; and signal means coupled to at least one of said row-addressing means and said column-addressing means and coupled to said M current switches for providing a signal to said M current switches to cause each current switch to switch current from the standard current-source word-line conductor for the corresponding row to the additional word-line conductor for said corresponding row, whereby said information is erased from said cells and said predetermined new pattern of information is entered into said cells.

Claim 21

An electronic circuit for information storage having a capability for simultaneously erasing the present information contained in said electronic circuit and entering a predetermined new pattern of information into said electronic circuit, said electronic circuit comprising: a plurality of bistable semiconductor cells arranged in an array of M word rows and N bit columns, where M and N are positive integers and N is greater than one, each of said cells having two transistors arranged in a bistable configuration for information bit storage, thereby to permit each cell to exist in one of two possible states, said two transistors being designated as a left-hand transistor and a right-hand transistor, and each cell having an additional current conducting region formed as part of a selected transistor of said two transistors in said cell, the predetermined new information bit in said cell being defined by the state of said cell when said selected transistor is conducting; M upper word-line conductors corresponding on a one-to-one basis to said M rows, each upper word-line conductor being coupled to the cells in the corresponding row; row-addressing means connected to said M upper word-line conductors for addressing at least one selected row; M standard current-source word-line conductors corresponding on a one-to-one basis to said M rows, each standard current-source word-line conductor being coupled to the cells in the corresponding row for conducting current to the cells in said corresponding row to sustain the states of said cells in said corresponding row; N left-hand bit-line conductors corresponding on a one-to-one basis to said N columns, each left-hand bit-line conductor being coupled to the left-hand transistors in the cells of the corresponding column; N right-hand bit-line conductors corresponding to a one-to-one basis to said N columns, each right-hand bit-line conductor being coupled to the right-hand transistors in the cells of the corresponding column; column-addressing means connected to said 2N bit-line conductors for addressing at least one selected column; M additional word-line conductors corresponding on a one-to-one basis to said M rows, each additional word-line conductor being coupled to the selected transistors in the cells of the corresponding row through the additional current-conducting regions in the cells of said corresponding row; M current switches corresponding on a one-to-one basis to said M rows, each current switch being coupled to the standard current-source word-line conductor for the corresponding row and being coupled to the additional word-line conductor for said corresponding row for switching current from said standard current-source word-line conductor for said corresponding row to said additional word-line conductor for said corresponding row; and signal means coupled to at least one of said row-addressing means and said column-addressing means and coupled to said M current switches for providing a signal to said M current switches to cause each current switch to switch current from the standard current-source word-line conductor for the corresponding row to the additional word-line conductor for said corresponding row, whereby said information is erased from said cells and said predetermined new pattern of information is entered into said cells.

Claim 22

An electronic circuit according to claim 14 or 15 and further including: at least one word-line current source coupled to said M current switches for providing current either to said cells through said M standard current-source word-line conductors or to said selected transistors through said M additional word-conductors; and at least one bit-line current source coupled to said 2N bit-line conductors for providing current through said 2N bit-line conductors to said cells.

Claim 23

An electronic circuit according to claim 14 or 15 wherein said signal means are coupled to both said row-addressing means and said column-addressing means.

Claim 24

An electronic circuit according to claim 14 or 15 wherein said two transistors in each of said cells are bipolar transistors and said additional current-conducting region in each of said cells is an emitter region.

Claim 25

An electronic circuit according to claim 18 wherein each of said M current switches includes: a third bipolar transistor, the collector of said third transistor being connected to the additional word-line conductor for the corresponding row and the base of said third transistor being coupled to said signal means; a fourth bipolar transistor, the collector of said fourth transistor being connected to the standard current-source word-line conductor for said corresponding row, the base of said fourth transistor being connected to a first word-line current source of said at least one word-line current source, and the emitter of said fourth transistor being connected to the emitter of said third transistor; and a resistor connected between a second word-line current source of said at least one word-line current source and the interconnected emitters of said third and fourth transistors.

Claim 26

An electronic circuit according to claim 14 or 15 wherein: said row-addressing means includes word-line address circuitry and M word-line drivers corresponding on a one-to-one basis to said M rows, each word-line driver being coupled to said word-line address circuitry and being coupled to the upper word-line conductor for the corresponding row; and said column-addressing means includes bit-line address circuitry and N sense amplifiers corresponding on a one-to-one basis to said N columns, each sense amplifier being coupled to said bit-line address circuitry and being coupled to the two bit-line conductors for the corresponding column.

Claim 27

An electronic circuit according to claim 14 or 15 wherein a coupling transistor is used to couple one of said address circuitries to said signal means, the base of said coupling transistor being connected to said signal means, the emitter of said coupling transistor being connected to said address circuitry, the collector of said coupling transistor being connected to the leading cathode of a double diode, and the trailing anode of said double diode being connected to an external current source.