Associative memory circuit

Claim 2

In an associative memory circuit having a plurality of memory cells arranged in a matrix of columns of words and rows of bits for storing, retrieving and comparing binary information, a memory cell comprised of: a. a transistorized bistable multivibrator; b. input means for addressing the cell; c. input means for writing binary information into the cell; d. output means for reading binary information out of the cell; e. means for comparing binary information stored in the cell to other binary information; wherein f. the transistorized bistable multivibrator is comprised of four transistors each having a base contact, a collector contact and a plurality of emitter contacts interconnected to form two stages, the base contact of the first transistor being cross-coupled to the collector contact of the second transistor, the base contact of said second transistor being cross-coupled to the collector contact of said first transistor, the base contact of the third transistor being cross-coupled to the collector contact of the fourth transistor, the base contAct of said fourth transistor being cross-coupled to the collector contact of said third transistor and the emitter contacts of said transistors providing the input and output means of said cells.

Claim 3

The memory cell of claim 1 including means for coupling the collector contacts of each of said transistors to a collector voltage supply.

Claim 4

In an associative memory circuit having a plurality of memory cells arranged in a matrix of columns of words and rows of bits for storing, retrieving and comparing binary information, a memory cell comprised of a transistorized bistable multivibrator comprised of first and second transistors each having a base contact, a collector contact and a plurality of emitter contacts, the base contact of said first transistor being cross-coupled to the collector contact of said second transistor, the base contact of said second transistor being cross-coupled to the collector contact of said first transistor and the emitter contacts of said transistors providing input and output means of said cells comprising: a. column input means for addressing a word; b. row input means for selectively programming an individual cell representing a bit of the addressed word to perform a binary function; c. output means for reading binary information out of said selected cell; d. input means for introducing other binary information into said memory cell; e. output means for determining whether the binary information stored in said memory cell is equivalent to said other information; f. means for applying a relatively low voltage to selected ones of said plurality of emitters representing a binary ''''0''''; g. means for applying a relatively high voltage to other selected ones of said plurality of emitters representing a binary ''''1''''; and h. means for applying a reference voltage intermediate said low voltage and said high voltage to remaining ones of said plurality of emitters, whereby a current appears on one of said remaining emitters if the binary function is a binary ''''1.''''

Claim 5

In an associative memory circuit having a plurality of memory cells arranged in a matrix of columns of words and rows of bits for storing, retrieving and comparing binary information, a memory cell comprised of a transistorized bistable multivibrator comprised of first and second transistors each having a base contact, a collector contact and a plurality of emitter contacts, the base contact of said first transistor being cross-coupled to the collector contact of said second transistor, the base contact of said second transistor being cross-coupled to the collector contact of said first transistor and the emitter contacts of said transistors providing input and output means of said cells comprising: a. column input means for addressing a word; b. row input means for selectively programming an individual cell representing a bit of the addressed word to perform a binary function; c. output means for reading binary information out of said selected cell; d. input means for introducing other binary information into said memory cell; e. output means for determining whether the binary information stored in said memory cell is equivalent to said other information; f. means for applying a relatively low voltage to selected ones of said plurality of emitters representing a binary ''''0''''; g. means for applying a relatively high voltage to other selected ones of said plurality of emitters representing a binary ''''1''''; and h. means for applying a reference voltage intermediate said low voltage and said high voltage to remaining ones of said plurality of emitters, whereby a current appears on one of said remaining emitters if the binary function is a binary ''''1.''''

Claim 6

The memory cell of claim 3 including means for coupling the collector contacts of each of said transistors to a collector voltage supply.

Claim 7

In an associative memory circuit having a plurality of memory cells arranged in a matrix of columns of words and rows of bits for storing, retrieving and comparing binary information, a memory cell comprised of a transistorized bistable multivibrator comprised of first and second transistors each having a base contact, a collector contact and a plurality of emitter contacts, the base contact of said first transistor being cross-coupled to the collector contact of said second transistor and the base contact of said second transistor being cross-coupled to the collector contact of said first transistor and the emitter contacts of said transistors providing input and output means of said cells comprising: a. column input-output means for addressing a word and retrieving information from a cell; b. first and second row input-output means for selectively programming and retrieving information from an individual cell representing a bit of the addressed word; c. means for applying a relatively low voltage to selected ones of said plurality of emitters representing a binary ''''0''''; d. means for applying a relatively high voltage to other selected ones of said plurality of emitters representing a binary ''''1''''; e. means for applying a first reference voltage intermediate said low voltage and said high voltage to other selected ones of said plurality of emitters; and f. means for applying a second reference voltage intermediate said first reference voltage and said high voltage to the remaining ones of said plurality of emitters, whereby a current or noncurrent condition occurs on certain ones of the emitters representing the result of a programmed function.

Claim 8

In an associative memory circuit having a plurality of memory cells arranged in a matrix of columns of words and rows of bits for storing, retrieving and comparing binary information, a memory cell comprised of a transistorized bistable multivibrator comprised of first and second transistors each having a base contact, a collector contact and a plurality of emitter contacts, the base contact of said first transistor being cross-coupled to the collector contact of said second transistor and the base contact of said second transistor being cross-coupled to the collector contact of said first transistor and the emitter contacts of said transistors providing input and output means of said cells comprising: a. column input-output means for addressing a word and retrieving information from a cell; b. first and second row input-output means for selectively programming and retrieving information from an individual cell representing a bit of the addressed word; c. means for applying a relatively low voltage to selected ones of said plurality of emitters representing a binary ''''0''''; d. means for applying a relatively high voltage to other selected ones of said plurality of emitters representing a binary ''''1''''; e. means for applying a first reference voltage intermediate said low voltage and said high voltage to other selected ones of said plurality of emitters; and f. means for applying a second reference voltage intermediate said first reference voltage and said high voltage to the remaining ones of said plurality of emitters, whereby a current or noncurrent condition occurs on certain ones of the emitters representing the result of a programmed function.

Claim 9

The memory cell of claim 5 including means for coupling the collector contacts of each of said transistors to a collector voltage supply.

Claim 10

In an associative memory circuit having a plurality of memory cells arranged in a matrix of columns of words and rows of bits for storing, retrieving and comparing binary information, a memory cell comprised of a transistorized dual-stage bistable multivibrator having four transistors each transistor having a base contact, a collector contact and a plurality of emitter contacts, the base contact of the first transistor being cross-coupled to the collector contact of the second transistor, the base contact of the second transistor being cross-coupled to the collector contact of the first transistor, the base contact of the third transistor being cross-coupled to the collector contact of the fourth transistor, the base contact of the fourth transistor being cross-coupled to the collector contact of the third transistor and the emitter contacts of said transistors providing input and output means of said cells comprising: a. column input means for addressing a word; b. row input-output means for selectively programming an individual cell representing a bit of the addressed word and reading information out of said cell; c. input means for writing binary information into said cell; d. input means for introducing other binary information into said memory cell; e. output means for determining whether the binary information stored in said memory cell is equivalent to said other information; f. means for applying a relatively low voltage to selected ones of said plurality of emitters representing a binary ''''0''''; g. means for applying a relatively high voltage to other selected ones of said plurality of emitters representing a binary ''''1''''; h. means for applying a reference voltage intermediate said low voltage and said high voltage to the remaining ones of said plurality of emitters, whereby a current or noncurrent condition occurs on certain ones of said remaining emitters representing the result of a programmed function.

Claim 11

In an associative memory circuit having a plurality of memory cells arranged in a matrix of columns of words and rows of bits for storing, retrieving and comparing binary information, a memory cell comprised of a transistorized dual-stage bistable multivibrator having four transistors each transistor having a base contact, a collector contact and a plurality of emitter contacts, the base contact of the first transistor being cross-coupled to the collector contact of the second transistor, the base contact of the second transistor being cross-coupled to the collector contact of the first transistor, the base contact of the third transistor being cross-coupled to the collector contact of the fourth transistor, the base contact of the fourth transistor being cross-coupled to the collector contact of the third transistor and the emitter contacts of said transistors providing input and output means of said cells comprising: a. column input means for addressing a word; b. row input-output means for selectively programming an individual cell representing a bit of the addressed word and reading information out of said cell; c. input means for writing binary information into said cell; d. input means for introducing other binary information into said memory cell; e. output means for determining whether the binary information stored in said memory cell is equivalent to said other information; f. means for applying a relatively low voltage to selected ones of said plurality of emitters representing a binary ''''0''''; g. means for applying a relatively high voltage to other selected ones of said plurality of emitters representing a binary ''''1''''; h. means for applying a reference voltage intermediate said low voltage and said high voltage to the remaining ones of said plurality of emitters, whereby a current or noncurrent condition occurs on certain ones of said remaining emitters representing the result of a programmed function.

Claim 12

The memory cell of claim 7 including means for coupling the collector contacts of each of said transistors to a collector voltage supply.