Modulation circuit of a digital-to-analog converter

Claim 3

The method of claim 1 wherein said digital data codes are binary codes.

Claim 4

The method of claim 1 wherein said code train of pulses are of unitary voltage magnitude.

Claim 5

The method of claim 1 wherein said width modulated pulses developed by said step of pulse width modulating are produced at equidistant intervals in said predetermined time period.

Claim 6

The method of claim 5 wherein the pulses developed by said step of pulse number modulating, when less than said maximum number, are produced at only certain of said equidistant intervals.

Claim 7

The method of claim 1 wherein M is equal to two and N is equal to three.

Claim 8

The method of claim 1 wherein a said digital data code representing a maximum number representable is converted by said step of converting into a single pulse having a width substantially equal to said predetermined time duration.

Claim 9

The method of claim 1 wherein said step of pulse width modulating locates all but one of said width modulated pulses in juxtaposition to the location of a one of said maximum number of pulses developed by said step of pulse number modulating.

Claim 10

An analog to digital converter for converting a data train of digital data codes into an analog representation thereof, said digital data codes including an N bit higher order code portion and an M bit lower order code portion, where N and M are natural numbers, comprising: means for converting each said digital data code into a code train of pulses, said code train of pulses being developed over a predetermined time period, said means for converting converting a said digital data code representative of zero into an absence of pulses during said predetermined time period; and means, operatively connected to said means for converting, for integrating each said code train of pulses into an analog value associated therewith to thereby develop an analog waveform from said data train; said means for converting comprising, pulse number modulation means, receiving said M bit lower order code portion of each said digital data code, for developing a number of pulses in said code train of pulses equal to the digital value of said M bit lower order code portion, pulse width modulation means, receiving said N bit higher order code portion of said digital data code, for developing a plurality of width modulated pulses one greater in number than the maximum number of pulses developed by said pulse number modulation means, each of said plurality of width modulated pulses increasing in width in relation to the digital value of said N bit higher order code portion.

Claim 11

An analog to digital converter for converting a data train of digital data codes into an analog representation thereof, said digital data codes including an N bit higher order code portion and an M bit lower order code portion, where N and M are natural numbers, comprising: means for converting each said digital data code into a code train of pulses, said code train of pulses being developed over a predetermined time period, said means for converting converting a said digital data code representative of zero into an absence of pulses during said predetermined time period; and means, operatively connected to said means for converting, for integrating each said code train of pulses into an analog value associated therewith to thereby develop an analog waveform from said data train; said means for converting comprising, pulse number modulation means, receiving said M bit lower order code portion of each said digital data code, for developing a number of pulses in said code train of pulses equal to the digital value of said M bit lower order code portion, pulse width modulation means, receiving said N bit higher order code portion of said digital data code, for developing a plurality of width modulated pulses one greater in number than the maximum number of pulses developed by said pulse number modulation means, each of said plurality of width modulated pulses increasing in width in relation to the digital value of said N bit higher order code portion.

Claim 12

The converter of claim 9 wherein said digital data codes are binary codes.

Claim 13

The converter of claim 9 wherein said code train of pulses are of unitary voltage magnitude.

Claim 14

The converter of claim 9 wherein said width modulated pulses developed by said pulse width modulation means are produced thereby at equidistant intervals in said predetermined time period.

Claim 15

The converter of claim 12 wherein the pulses developed by said pulse number modulation means, when less than said maximum number, are produced at only certain of said equidistant intervals.

Claim 16

The converter of claim 9 wherein M is equal to two and N is equal to three.

Claim 17

The converter of claim 9 wherein said means for converting converts a said digital data code representing a maximum representable number into a single pulse of a width substantially equal to said predetermined time duration.

Claim 18

The converter of claim 9 further comprising timing counter means for developing timing signals, said timing counter means supplying said timing signals to said means for converting to time the location of said number of pulses developed by said pulse number modulation means and the location and width of said width modulated pulses developed by said pulse width modulation means.

Claim 19

The converter of claim 9 wherein said pulse width modulation means locates all but one of said width modulated pulses in juxtaposition to the location of a one of said maximum number of pulses developed by said pulse number modulation means.

Claim 20

A modulation circuit of a digital to analog converter for converting a digital data code into a pulse train of unitary pulses for integration to develop an analog value representative thereof comprising: pulse number modulation means for developing an output having a varying number of pulses corresponding to the values of selected digital data bits of said digital data code during a predetermined conversion period; pulse width modulation means for developing an output including pulses during said predetermined conversion period, said predetermined conversion period being divided into a predetermined number of segments, each said segment having an associated pulse developed therein, said pulses being developed of widths determined by the value of the remaining digital data bits; and combination means for combining the outputs of the pulse number modulation means and the pulse width modulation means by positioning a pulse from the output of the pulse width modulation means in juxtaposition with a pulse from the output of the pulse number modulation means to produce a resultant said pulse train, said resultant said pulse train consisting of a varying number of pulses for lower range and high range values of said digital data code and a constant number of pulses for medium range data values of said digital data code.

Claim 21

A modulation circuit of a digital to analog converter for converting a digital data code into a pulse train of unitary pulses for integration to develop an analog value representative thereof comprising: pulse number modulation means for developing an output having a varying number of pulses corresponding to the values of selected digital data bits of said digital data code during a predetermined conversion period; pulse width modulation means for developing an output including pulses during said predetermined conversion period, said predetermined conversion period being divided into a predetermined number of segments, each said segment having an associated pulse developed therein, said pulses being developed of widths determined by the value of the remaining digital data bits; and combination means for combining the outputs of the pulse number modulation means and the pulse width modulation means by positioning a pulse from the output of the pulse width modulation means in juxtaposition with a pulse from the output of the pulse number modulation means to produce a resultant said pulse train, said resultant said pulse train consisting of a varying number of pulses for lower range and high range values of said digital data code and a constant number of pulses for medium range data values of said digital data code.