US4096475A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for the conversion of a digital signal to an analog signal
Assignee: US Philips Corp
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Filing: 1976-06-30
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Granted: 1978-06-20
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Expires: 1996-06-30
Abstract
Abstract A digital-to-analog converter using a combined pulse rate and pulse width modulation of an output signal of a circuit for providing a digital signal to be converted to a periodically occurring series of digital comparison signals to be obtained by a proper choice of a particular series. The digital-to-analog converter has a very small error which, due to its low temperature sensitivity, is particularly suitable for tuning circuits of television receivers.
Inventors
- 👤 Kian Kie Ong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:57
CPC Classifications
H; H03; H03J; H03J5/00; H03J5/02; H03J5/0245; H03J5/0254; H03M; H03M1/00; H03M1/66; H03M1/661
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
328 words
A tuning system comprising a circuit for the conversion of a digital signal to an analog signal comprising a comparator and a generator, said comparator having inputs for comparing the value of the digital signal which corresponds to a digital number (A = A n-1 . . . A O ) to be converted, to the value of a digital comparison signal which corresponds to a periodically occurring series of n-digit comparison numbers (C = C n-1 . . . C O ) produced by said generator, and an output; said generator being connected to said comparator and adapted for the generation of a signal that corresponds to a series of digital comparison numbers of which for each subsequent comparison number (C = C n-1 . . . C O ) the most significant first m digits (C n-1 . . . C n-m ) count through a series of numbers (D = D m-1 . . . D O ) each of which numbers monotonically increases or decreases each time in value by one and corresponds to the m-counter digits of a number (B m-1 . . . B O ), the least significant (n-m) digits of said comparison number forming a digital number (E = E n-m-1 . . . E O ) whose digits form an inverted order of the digits of a number (B n-1 . . . B m ) of (n-m) digits, which each time increases or decreases respectively by one when the number series (C n-1 . . . C n-m ) of the first m figures, reckoned in sequence of decreasing significance of the comparison number (C), has been counted through, with the condition that n ≧ 3, m ≠ 1, m ≠ n, n and m be positive integers; a low pass filter having an input connected to said output of said comparator and an output; and a tuning unit connected to the output of said low pass filter.
Claim 2
Dependent Claim
328 words
A tuning system comprising a circuit for the conversion of a digital signal to an analog signal comprising a comparator and a generator, said comparator having inputs for comparing the value of the digital signal which corresponds to a digital number (A = A n-1 . . . A O ) to be converted, to the value of a digital comparison signal which corresponds to a periodically occurring series of n-digit comparison numbers (C = C n-1 . . . C O ) produced by said generator, and an output; said generator being connected to said comparator and adapted for the generation of a signal that corresponds to a series of digital comparison numbers of which for each subsequent comparison number (C = C n-1 . . . C O ) the most significant first m digits (C n-1 . . . C n-m ) count through a series of numbers (D = D m-1 . . . D O ) each of which numbers monotonically increases or decreases each time in value by one and corresponds to the m-counter digits of a number (B m-1 . . . B O ), the least significant (n-m) digits of said comparison number forming a digital number (E = E n-m-1 . . . E O ) whose digits form an inverted order of the digits of a number (B n-1 . . . B m ) of (n-m) digits, which each time increases or decreases respectively by one when the number series (C n-1 . . . C n-m ) of the first m figures, reckoned in sequence of decreasing significance of the comparison number (C), has been counted through, with the condition that n ≧ 3, m ≠ 1, m ≠ n, n and m be positive integers; a low pass filter having an input connected to said output of said comparator and an output; and a tuning unit connected to the output of said low pass filter.
Claim 3
Dependent Claim
221 words
A system as claimed in claim 1, wherein the generator is a counter whose first figure (B O ) reckoned in sequence of increasing significance of the position of the counter output (B = B n-1 . . . B O ) is compared in the comparator to the (m + 1) th figure (A n-m ) reckoned in the direction of increasing significance of a digital number (A) to be converted, the second figure (B 1 ) of the counter position (B) is compared to the (m + 2) th figure (A n-m+1 ) of the digital number (A) to be converted and so on, the m th figure (B m-1 ) of the counter position (B) to the n th figure (A n-1 ) of the digital number (A) to be converted, the (m + 1) th figure (B m ) of the counter position (B) to the (n-m) th figure (A n-m-1 ) of the digital number (A) 1 , the (n-m+ 1) th figure (B m+1 ) of the counter position (B) to the (n-m-2) th figure (A n-m ) of the digital number (A) and so on, so that the n th figure (B n-1 ) of the counter position is compared to the first figure (A O ) of the digital number to be converted.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-19 | 1981-12-19 | 1982-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-19 | 1985-12-19 | 1986-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-19 | 1989-12-19 | 1990-06-20 | $7700.00 | Window Closed / Lapsed |