US4467319A
Expired / Lapsed
US
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Signal conversion circuit
Assignee: Nakamichi Corp
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Filing: 1982-03-22
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Granted: 1984-08-21
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Expires: 2002-03-22
Abstract
Abstract This invention relates to a signal conversion circuit, and more particularly to a signal conversion circuit to convert a digital signal sampled in synchronism with a sampling pulse into a pulse width signal having a pulse width corresponding to the digital value of the digital signal. A first counter is preset to a first count value corresponding to the digital value of the sampled digital signal and begins to count a first clock signal having a predetermined pulse period from the first count value. A second counter is preset to a second count value which is a complement of the first count value and begins to count a second clock signal having a pulse period twice as many as that of the first clock signal from the second count value in response to the detection of a full count of the first counter. A rising edge of the pulse width signal responds to the detection of the full count of the first counter and a falling edge thereof responds to the detection of a full count of the second counter whereby the center of a pulse width of the pulse width signal has a predetermined phase relation to the sampling pulse.
Inventors
- 👤 Gohji Uchikoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 07:31
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/82
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
218 words
A signal conversion circuit to convert a digital signal sampled in synchronism with a sampling pulse into a pulse width signal having a pulse width corresponding to the digital value of said digital signal and comprising; a first counter to be preset to a first count value corresponding to a digital value of said digital signal and to begin to count a first clock signal having a predetermined pulse period from said first count value; first detection means to detect a full count of said first counter; a second counter to be preset to a second count value which is a complement of said first count value and to begin to count a second clock signal having a pulse period twice as many as that of said first clock signal from said second count value in response to the detection of said full count of said first counter by said first detection means; second detection means to detect a full count of said second counter; and a rising edge of said pulse width signal responding to the detection by said first detection means and a falling edge thereof responding to the detection by said second detection means whereby the center of a pulse width of said pulse width signal has a predetermined phase relation to said sampling pulse.
Claim 2
Dependent Claim
218 words
A signal conversion circuit to convert a digital signal sampled in synchronism with a sampling pulse into a pulse width signal having a pulse width corresponding to the digital value of said digital signal and comprising; a first counter to be preset to a first count value corresponding to a digital value of said digital signal and to begin to count a first clock signal having a predetermined pulse period from said first count value; first detection means to detect a full count of said first counter; a second counter to be preset to a second count value which is a complement of said first count value and to begin to count a second clock signal having a pulse period twice as many as that of said first clock signal from said second count value in response to the detection of said full count of said first counter by said first detection means; second detection means to detect a full count of said second counter; and a rising edge of said pulse width signal responding to the detection by said first detection means and a falling edge thereof responding to the detection by said second detection means whereby the center of a pulse width of said pulse width signal has a predetermined phase relation to said sampling pulse.
Claim 3
Dependent Claim
31 words
A signal conversion circuit as set forth in claim 1, wherein said first count value is said digital value while said second count value is a complement of said digital value.
Claim 4
Dependent Claim
19 words
A signal conversion circuit as set forth in claim 2, wherein said first and second counters are up counters.
Claim 5
Dependent Claim
31 words
A signal conversion circuit as set forth in claim 1, wherein said first count value is a complement of said digital value while said second count value is said digital value.
Claim 6
Dependent Claim
19 words
A signal conversion circuit as set forth in claim 4, wherein said first and second counters are down counters.
Claim 7
Dependent Claim
53 words
A signal conversion circuit as set forth in claim 1, wherein said first and second detection means comprise a NAND gate to receive the outputs from the corresponding counter and a D-type flip-flop circuit to receive the output from said NAND gate and to generate the output from a Q output terminal thereof.
Claim 8
Dependent Claim
48 words
A signal conversion circuit as set forth in claim 6, and further comprising a JK flip-flop circuit to receive the output from a Q output terminal of said D-type flip-flop circuit of said first detection means and to generate said second clock signal from an output terminal thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-21 | 1988-02-20 | 1988-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-21 | 1992-02-20 | 1992-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-21 | 1996-02-20 | 1996-08-21 | $7700.00 | Window Closed / Lapsed |